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1,506 Commits 9 Branches 14 Tags 11 MiB
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8 Commits

Author SHA1 Message Date
Florent Kermarrec 877bc4b45e targets: Use full imports (vendor_board). 2022-05-02 12:55:11 +02:00
Florent Kermarrec 575d681891 targets: Use "" for strings. 2022-04-21 15:48:29 +02:00
Florent Kermarrec 4fbf2fc7de targets: Replace self.add_wb_master with self.bus.add_master. 2022-04-21 15:32:19 +02:00
Florent Kermarrec a611f035d6 targets: Move CRG before SoCCore init (More logical and simplify some specific reset schemes) and switch SoCCore to one line when possible. 
Moving CRG simplify reset with NaxRiscv debug module and is in fact more logical.
Also do some minor updates/cosmetic changes while touching CRG/SoCCore.
 2022-04-21 12:19:45 +02:00
Florent Kermarrec 9d452b0d74 targets: Create target_group for target arguments. 2022-03-21 18:37:40 +01:00
Florent Kermarrec cc8da9d341 targets: Simplify imports and switch to LiteXSocArgumentParser. 
CPU parameters are now selectively exposed to the user:
./digilent_arty.py --cpu-type=vexriscv_smp --help will show VexRiscv-SMP parameters.
./digilent_arty.py --cpu-type=naxriscv --help will show NaxRiscv parameters.
 2022-03-21 16:59:40 +01:00
Florent Kermarrec 773444a7dd targets: Switch to get_bios_filename/get_bitstream_filename. 2022-03-17 09:21:05 +01:00
Ilia Sergachev 85397818d9 add Xilinx ZCU216 support 2022-02-21 19:14:13 +01:00