5 Commits

Author	SHA1	Message	Date
Sergiu Mosanu	a1d830566a	added ddr4_sdram_c1 constraints	2021-02-01 12:22:41 -05:00
Sergiu Mosanu	1916677dc9	use VREF constraint for DDR4 C0	2021-01-28 19:58:38 -05:00
Sergiu Mosanu	84656a9c2e	re-compare and adjust to u250	2021-01-26 23:03:09 -05:00
Sergiu Mosanu	7a738245af	fix bitstream problem	2021-01-14 21:53:25 -05:00
Sergiu Mosanu	5a73eb0b6d	initiate target and platform for alveo_u280 board	2021-01-14 18:35:43 -05:00