575d681891
targets: Use "" for strings.
2022-04-21 15:48:29 +02:00
4fbf2fc7de
targets: Replace self.add_wb_master with self.bus.add_master.
2022-04-21 15:32:19 +02:00
a611f035d6
targets: Move CRG before SoCCore init (More logical and simplify some specific reset schemes) and switch SoCCore to one line when possible.
...
Moving CRG simplify reset with NaxRiscv debug module and is in fact more logical.
Also do some minor updates/cosmetic changes while touching CRG/SoCCore.
2022-04-21 12:19:45 +02:00
9d452b0d74
targets: Create target_group for target arguments.
2022-03-21 18:37:40 +01:00
cc8da9d341
targets: Simplify imports and switch to LiteXSocArgumentParser.
...
CPU parameters are now selectively exposed to the user:
./digilent_arty.py --cpu-type=vexriscv_smp --help will show VexRiscv-SMP parameters.
./digilent_arty.py --cpu-type=naxriscv --help will show NaxRiscv parameters.
2022-03-21 16:59:40 +01:00
773444a7dd
targets: Switch to get_bios_filename/get_bitstream_filename.
2022-03-17 09:21:05 +01:00
3f58df9974
platforms/targets: Fix typos.
2022-02-14 17:26:46 +01:00
bbf13f4439
zedboard: remove a hack
2022-01-19 02:41:11 +01:00
4f4d47dcdd
zedboard: correct memory map
2022-01-19 02:40:54 +01:00
fccb952c4b
target: Remove ident_version=True no longer required.
2022-01-18 17:13:02 +01:00
144c0dc27e
digilent_zedboard: +x.
2022-01-06 09:38:19 +01:00
53dc00eab7
targets/parser: Rely on argparse.ArgumentDefaultsHelpFormatter to provide default in help description.
...
Also do minor adjustments while doing this.
2022-01-05 17:06:40 +01:00
bc3c42ab5f
zedboard: disable soc uart for all variants (zynq does not need it, for soft cpus there are no pins)
2021-12-22 03:28:13 +01:00
53ce00b3fd
zedboard: add target with bios on arm zynq cpu
2021-12-22 03:14:13 +01:00
Florent Kermarrec
Ilia Sergachev