Florent Kermarrec
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47bdf5f759
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targets: Use new CSR automatic allocation (self.add_csr will still work but is no longer required).
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2021-03-25 10:11:24 +01:00 |
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Florent Kermarrec
|
5995769b46
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targets: Switch to soc_core_args/soc_core_argdict (instead of soc_sdram that is now deprecated, but still supported for now).
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2021-03-24 17:22:51 +01:00 |
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Florent Kermarrec
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d73bd2f7ce
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targets/xilinx: add comment on sys_clk to pll.clkin false path.
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2021-01-07 08:01:54 +01:00 |
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Florent Kermarrec
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1ac1c6857f
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targets/xilinx: add false path constraint between sys_clk and pll.clkin.
The SoC reset added recently creates a path between sys_clk and pll.clkin
clock domains that is reported by the tools but that can be safely ignored.
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2021-01-07 00:02:46 +01:00 |
Nathaniel R. Lewis
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389b623fe2
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targets/litefury: new target
LiteFury is an Artix-7 development board in the M.2 form factor
for PCIe accelerator development. It's similar to the Aller but
with an xc7a100t rather than an xc7a200t and no TPM module.
https://rhsresearch.com/collections/rhs-public/products/litefury
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2020-11-19 21:52:14 -08:00 |