Florent Kermarrec
|
8792dd8e53
|
target/analog_pocket: Remove debug (Will be investigated externally).
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2023-10-27 15:32:36 +02:00 |
Gwenhael Goavec-Merou
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a6f3c5276e
|
target/xxx: remove with-jtagbone, add_jtagbone and deal with case where jtagbone is required inconditionnally
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2023-10-23 17:16:57 +02:00 |
|
Florent Kermarrec
|
eae62a60ac
|
target/analog_pocket: Fix.
|
2023-10-17 21:40:46 +02:00 |
|
Florent Kermarrec
|
cc19078650
|
targets/analog_pocket: Disable debug for CI.
|
2023-10-17 15:23:58 +02:00 |
|
Florent Kermarrec
|
f86ba2dea0
|
targets/analog_pocket: Add debug code for framebuffer (wip).
|
2023-10-17 13:18:07 +02:00 |
|
Florent Kermarrec
|
ec2f9480b8
|
targets/analog_pocket: Fix indent on videophy/cores.
|
2023-10-09 11:59:32 +02:00 |
|
Florent Kermarrec
|
6386f290e9
|
targets/analog_pocket: Add --video-colorbars/video-terminal/video-framebuffer arguments.
|
2023-10-09 10:59:15 +02:00 |
|
Florent Kermarrec
|
dec25b7ce9
|
targets/analog_pocket: Add initial Video support.
From https://github.com/tpwrules/pocket_linux.
|
2023-10-09 10:14:00 +02:00 |
|
Florent Kermarrec
|
7359a331eb
|
analog_pocket: Add 1:2 (HalfRate) SDRAM support.
|
2023-10-06 19:25:42 +02:00 |
|
Florent Kermarrec
|
3d7a1dd152
|
analog_pocket: +x.
|
2023-10-02 16:20:09 +02:00 |
|
Florent Kermarrec
|
3df677cfeb
|
Add initial Analog Pocket platform/target with Clk/SDRAM, able to run a simple SoC with SDRAM over JTAG-UART.
$ ./analog_pocket.py --uart-name=jtag_uart --build --load
$ litex_term jtag --jtag-config=openocd_usb_blaster.cfg
__ _ __ _ __
/ / (_) /____ | |/_/
/ /__/ / __/ -_)> <
/____/_/\__/\__/_/|_|
Build your hardware, easily!
(c) Copyright 2012-2023 Enjoy-Digital
(c) Copyright 2007-2015 M-Labs
BIOS built on Sep 21 2023 08:53:57
BIOS CRC passed (1e2b3f44)
LiteX git sha1: 7d738737
--=============== SoC ==================--
CPU: VexRiscv @ 50MHz
BUS: WISHBONE 32-bit @ 4GiB
CSR: 32-bit data
ROM: 128.0KiB
SRAM: 8.0KiB
L2: 8.0KiB
SDRAM: 64.0MiB 16-bit @ 50MT/s (CL-2 CWL-2)
MAIN-RAM: 64.0MiB
--========== Initialization ============--
Initializing SDRAM @0x40000000...
Switching SDRAM to software control.
Switching SDRAM to hardware control.
Memtest at 0x40000000 (2.0MiB)...
Write: 0x40000000-0x40200000 2.0MiB
Read: 0x40000000-0x40200000 2.0MiB
Memtest OK
Memspeed at 0x40000000 (Sequential, 2.0MiB)...
Write speed: 15.6MiB/s
Read speed: 22.1MiB/s
--============== Boot ==================--
Booting from serial...
Press Q or ESC to abort boot completely.
sL5DdSMmkekro
Timeout
No boot medium found
--============= Console ================--
litex>
|
2023-09-21 09:19:57 +02:00 |