Florent Kermarrec
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7c48af9b50
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tec0117: get SDRAM working and increase sys_clk_freq to 25MHz.
./tec0117.py --build --load
Still some FIXMEs but validate use of the embedded SDRAM with LiteDRAM/LiteX:
__ _ __ _ __
/ / (_) /____ | |/_/
/ /__/ / __/ -_)> <
/____/_/\__/\__/_/|_|
Build your hardware, easily!
(c) Copyright 2012-2020 Enjoy-Digital
(c) Copyright 2007-2015 M-Labs
BIOS built on Feb 1 2021 13:09:35
BIOS CRC passed (5abceb2e)
Migen git sha1: 40b1092
LiteX git sha1: f324f953
--=============== SoC ==================--
CPU: VexRiscv_Lite @ 25MHz
BUS: WISHBONE 32-bit @ 4GiB
CSR: 32-bit data
ROM: 24KiB
SRAM: 4KiB
L2: 0KiB
SDRAM: 8192KiB 16-bit @ 25MT/s (CL-2 CWL-2)
--========== Initialization ============--
Initializing SDRAM @0x40000000...
Switching SDRAM to software control.
Switching SDRAM to hardware control.
Memtest at 0x40000000 (2MiB)...
Write: 0x40000000-0x40200000 2MiB
Read: 0x40000000-0x40200000 2MiB
Memtest OK
Memspeed at 0x40000000 (2MiB)...
Write speed: 5MiB/s
Read speed: 6MiB/s
--============== Boot ==================--
Booting from serial...
Press Q or ESC to abort boot completely.
sL5DdSMmkekro
Timeout
No boot medium found
--============= Console ================--
litex> mem_list
Available memory regions:
ROM 0x00000000 0x6000
SRAM 0x01000000 0x1000
SPIFLASH 0x80000000 0x1000000
MAIN_RAM 0x40000000 0x800000
CSR 0x82000000 0x10000
litex> mem_test 0x40000000 0x800000
Memtest at 0x40000000 (8MiB)...
Write: 0x40000000-0x40800000 8MiB
Read: 0x40000000-0x40800000 8MiB
Memtest OK
litex>
|
2021-02-01 13:32:01 +01:00 |
|
Florent Kermarrec
|
51c5d69586
|
targets/tec0117: use custom CPU/ROM/SRAM config to minimize resources.
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2021-02-01 13:31:56 +01:00 |
|
Florent Kermarrec
|
538878ce13
|
tec0117: disable BIOS XIP from SPI Flash for now since not working (SPÏ Flash set to power down mode with bitstream?).
|
2021-02-01 13:31:51 +01:00 |
|
Florent Kermarrec
|
6cce07d9db
|
tec0117: add spiflash4x pins, rework flash function to flash both bitstream/bios.
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2021-02-01 13:31:44 +01:00 |
|
Florent Kermarrec
|
0831b33285
|
tec0117: fix copyrights.
|
2021-02-01 13:31:39 +01:00 |
|
Florent Kermarrec
|
abccd12058
|
tec0117: add initial SDRAM support for the embedded SDRAM of the SIP.
Still a WIP but able to do the P&R with modifications on LiteX to generate
the IO_PORT constraints but not the IO_LOC for the SDRAM pins.
|
2021-01-29 22:28:40 +01:00 |
|
Florent Kermarrec
|
edb99797aa
|
targets/tec0117: minor cleanups.
|
2021-01-29 21:25:10 +01:00 |
|
Florent Kermarrec
|
d42af3ea19
|
targets: add --sys-clk-freq support to all targets.
|
2020-11-12 18:07:28 +01:00 |
|
Florent Kermarrec
|
bd4e92ad13
|
targets: cleanup, uniformize build arguments between targets.
|
2020-11-12 11:46:00 +01:00 |
|
Florent Kermarrec
|
2b17dc1b89
|
target: add rst signal to CRG to allow full reset of the SoC on reboot command.
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2020-11-04 11:13:42 +01:00 |
|
Florent Kermarrec
|
ce14775dfb
|
targets/tec0117: move SerialFlashManager import to flash function.
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2020-11-04 09:30:31 +01:00 |
Pepijn de Vos
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18e5def9f2
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don't verify erase, very slow
|
2020-10-01 08:41:16 +02:00 |
|
Pepijn de Vos
|
81e4f1f158
|
add initial support for Trenz TEC0117 board
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2020-09-30 14:01:36 +02:00 |