tec0117: get SDRAM working and increase sys_clk_freq to 25MHz.
./tec0117.py --build --load
Still some FIXMEs but validate use of the embedded SDRAM with LiteDRAM/LiteX:
__ _ __ _ __
/ / (_) /____ | |/_/
/ /__/ / __/ -_)> <
/____/_/\__/\__/_/|_|
Build your hardware, easily!
(c) Copyright 2012-2020 Enjoy-Digital
(c) Copyright 2007-2015 M-Labs
BIOS built on Feb 1 2021 13:09:35
BIOS CRC passed (5abceb2e)
Migen git sha1: 40b1092
LiteX git sha1: f324f953
--=============== SoC ==================--
CPU: VexRiscv_Lite @ 25MHz
BUS: WISHBONE 32-bit @ 4GiB
CSR: 32-bit data
ROM: 24KiB
SRAM: 4KiB
L2: 0KiB
SDRAM: 8192KiB 16-bit @ 25MT/s (CL-2 CWL-2)
--========== Initialization ============--
Initializing SDRAM @0x40000000...
Switching SDRAM to software control.
Switching SDRAM to hardware control.
Memtest at 0x40000000 (2MiB)...
Write: 0x40000000-0x40200000 2MiB
Read: 0x40000000-0x40200000 2MiB
Memtest OK
Memspeed at 0x40000000 (2MiB)...
Write speed: 5MiB/s
Read speed: 6MiB/s
--============== Boot ==================--
Booting from serial...
Press Q or ESC to abort boot completely.
sL5DdSMmkekro
Timeout
No boot medium found
--============= Console ================--
litex> mem_list
Available memory regions:
ROM 0x00000000 0x6000
SRAM 0x01000000 0x1000
SPIFLASH 0x80000000 0x1000000
MAIN_RAM 0x40000000 0x800000
CSR 0x82000000 0x10000
litex> mem_test 0x40000000 0x800000
Memtest at 0x40000000 (8MiB)...
Write: 0x40000000-0x40800000 8MiB
Read: 0x40000000-0x40800000 8MiB
Memtest OK
litex>
This commit is contained in:
Florent Kermarrec
parent
51c5d69586
commit
7c48af9b50
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@ -15,8 +15,9 @@ from litex.build.openfpgaloader import OpenFPGALoader
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_io = [
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# Clk / Rst
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("clk12", 0, Pins("35"), IOStandard("LVCMOS33")),
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("rst", 0, Pins("77"), IOStandard("LVCMOS33")),
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("clk12", 0, Pins("35"), IOStandard("LVCMOS33")),
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("clk100", 0, Pins("63"), IOStandard("LVCMOS33")),
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("rst_n", 0, Pins("77"), IOStandard("LVCMOS33")),
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# Leds
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("user_led", 0, Pins("86"), IOStandard("LVCMOS33")),
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@ -31,7 +32,7 @@ _io = [
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# Serial
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("serial", 0,
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Subsignal("tx", Pins("15"), IOStandard("LVCMOS33")),
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Subsignal("rx", Pins("16"), IOStandard("LVCMOS33"))
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Subsignal("rx", Pins("16"), IOStandard("LVCMOS33")),
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),
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# SPIFlash
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@ -59,15 +60,15 @@ _io = [
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),
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# SDRAM (embedded in SIP, requires specific IO naming)
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("O_sdram_clk", 0, Pins(1), IOStandard("LVCMOS33")),
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("O_sdram_cke", 0, Pins(1), IOStandard("LVCMOS33")),
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("O_sdram_cs_n", 0, Pins(1), IOStandard("LVCMOS33")),
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("O_sdram_cas_n", 0, Pins(1), IOStandard("LVCMOS33")),
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("O_sdram_ras_n", 0, Pins(1), IOStandard("LVCMOS33")),
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("O_sdram_we_n", 0, Pins(1), IOStandard("LVCMOS33")),
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("O_sdram_dqm", 0, Pins(2), IOStandard("LVCMOS33")),
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("O_sdram_clk", 0, Pins(1), IOStandard("LVCMOS33")),
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("O_sdram_cke", 0, Pins(1), IOStandard("LVCMOS33")),
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("O_sdram_cs_n", 0, Pins(1), IOStandard("LVCMOS33")),
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("O_sdram_cas_n", 0, Pins(1), IOStandard("LVCMOS33")),
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("O_sdram_ras_n", 0, Pins(1), IOStandard("LVCMOS33")),
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("O_sdram_wen_n", 0, Pins(1), IOStandard("LVCMOS33")),
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("O_sdram_dqm", 0, Pins(2), IOStandard("LVCMOS33")),
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("O_sdram_addr", 0, Pins(12), IOStandard("LVCMOS33")),
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("O_sdram_ba", 0, Pins(2), IOStandard("LVCMOS33")),
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("O_sdram_ba", 0, Pins(2), IOStandard("LVCMOS33")),
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("IO_sdram_dq", 0, Pins(16), IOStandard("LVCMOS33")),
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]
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@ -22,15 +22,41 @@ from litex.soc.cores.led import LedChaser
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from litex_boards.platforms import tec0117
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from litedram.modules import M12L64322A # FIXME
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from litedram.modules import MT48LC4M16 # FIXME: use EtronTech reference.
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from litedram.phy import GENSDRPHY, HalfRateGENSDRPHY
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kB = 1024
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mB = 1024*kB
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# CRG ----------------------------------------------------------------------------------------------
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class _CRG(Module):
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def __init__(self, platform, sys_clk_freq):
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self.rst = Signal()
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self.clock_domains.cd_sys = ClockDomain()
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# # #
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# Clk / Rst
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clk100 = platform.request("clk100")
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rst_n = platform.request("rst_n")
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# Generate 25Mhz sys_clk_freq clock from 100MHz input clock, FIXME: use PLL.
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assert sys_clk_freq == 25e6
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self.clock_domains.cd_clk100 = ClockDomain()
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self.comb += self.cd_clk100.clk.eq(clk100)
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count = Signal(2)
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self.sync.clk100 += count.eq(count + 1)
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clk50 = count[0]
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clk25 = count[1]
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self.comb += self.cd_sys.clk.eq(clk25)
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self.comb += self.cd_sys.rst.eq(~rst_n | self.rst) # FIXME: use AsyncResetSynchronizer
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# BaseSoC ------------------------------------------------------------------------------------------
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class BaseSoC(SoCCore):
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mem_map = {**SoCCore.mem_map, **{"spiflash": 0x80000000}}
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def __init__(self, bios_flash_offset, sys_clk_freq=int(12e6), with_sdram=False, sdram_rate="1:1", **kwargs):
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def __init__(self, bios_flash_offset, sys_clk_freq=int(25e6), sdram_rate="1:1", **kwargs):
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platform = tec0117.Platform()
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# Use custom default configuration to fit in LittleBee.
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@ -49,7 +75,7 @@ class BaseSoC(SoCCore):
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**kwargs)
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# CRG --------------------------------------------------------------------------------------
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self.submodules.crg = CRG(platform.request("clk12"), ~platform.request("rst"))
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self.submodules.crg = _CRG(platform, sys_clk_freq)
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# SPI Flash --------------------------------------------------------------------------------
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self.add_spi_flash(mode="1x", dummy_cycles=8)
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@ -62,8 +88,8 @@ class BaseSoC(SoCCore):
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# linker = True)
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#)
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# SDR SDRAM (WIP) --------------------------------------------------------------------------
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if with_sdram:
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# SDR SDRAM --------------------------------------------------------------------------------
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if not self.integrated_main_ram_size:
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class SDRAMPads:
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def __init__(self):
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self.clk = platform.request("O_sdram_clk")
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@ -71,25 +97,23 @@ class BaseSoC(SoCCore):
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self.cs_n = platform.request("O_sdram_cs_n")
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self.cas_n = platform.request("O_sdram_cas_n")
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self.ras_n = platform.request("O_sdram_ras_n")
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self.we_n = platform.request("O_sdram_we_n")
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self.we_n = platform.request("O_sdram_wen_n")
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self.dm = platform.request("O_sdram_dqm")
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self.a = platform.request("O_sdram_addr")
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self.ba = platform.request("O_sdram_ba")
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self.dq = platform.request("IO_sdram_dq")
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sdram_pads = SDRAMPads()
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self.comb += sdram_pads.clk.eq(~ClockSignal("sys"))
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self.comb += sdram_pads.clk.eq(~ClockSignal("sys")) # FIXME: use phase shift from PLL.
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sdrphy_cls = HalfRateGENSDRPHY if sdram_rate == "1:2" else GENSDRPHY
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self.submodules.sdrphy = sdrphy_cls(sdram_pads, sys_clk_freq)
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self.add_sdram("sdram",
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phy = self.sdrphy,
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module = M12L64322A(sys_clk_freq, sdram_rate),
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module = MT48LC4M16(sys_clk_freq, sdram_rate), # FIXME.
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origin = self.mem_map["main_ram"],
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size = kwargs.get("max_sdram_size", 0x10000000),
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l2_cache_size = 0,
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l2_cache_min_data_width = kwargs.get("min_l2_data_width", 128),
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l2_cache_reverse = True
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l2_cache_size = 128,
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l2_cache_min_data_width = 256,
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)
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# Leds -------------------------------------------------------------------------------------
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@ -165,7 +189,7 @@ def main():
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parser.add_argument("--load", action="store_true", help="Load bitstream")
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parser.add_argument("--bios-flash-offset", default=0x80000, help="BIOS offset in SPI Flash (0x00000 default)")
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parser.add_argument("--flash", action="store_true", help="Flash Bitstream and BIOS")
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parser.add_argument("--sys-clk-freq", default=12e6, help="System clock frequency (default: 12MHz)")
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parser.add_argument("--sys-clk-freq", default=25e6, help="System clock frequency (default: 12MHz)")
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builder_args(parser)
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soc_core_args(parser)
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args = parser.parse_args()
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