mirror of
https://github.com/litex-hub/litex-boards.git
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7c48af9b50
./tec0117.py --build --load
Still some FIXMEs but validate use of the embedded SDRAM with LiteDRAM/LiteX:
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/ / (_) /____ | |/_/
/ /__/ / __/ -_)> <
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Build your hardware, easily!
(c) Copyright 2012-2020 Enjoy-Digital
(c) Copyright 2007-2015 M-Labs
BIOS built on Feb 1 2021 13:09:35
BIOS CRC passed (5abceb2e)
Migen git sha1: 40b1092
LiteX git sha1: f324f953
--=============== SoC ==================--
CPU: VexRiscv_Lite @ 25MHz
BUS: WISHBONE 32-bit @ 4GiB
CSR: 32-bit data
ROM: 24KiB
SRAM: 4KiB
L2: 0KiB
SDRAM: 8192KiB 16-bit @ 25MT/s (CL-2 CWL-2)
--========== Initialization ============--
Initializing SDRAM @0x40000000...
Switching SDRAM to software control.
Switching SDRAM to hardware control.
Memtest at 0x40000000 (2MiB)...
Write: 0x40000000-0x40200000 2MiB
Read: 0x40000000-0x40200000 2MiB
Memtest OK
Memspeed at 0x40000000 (2MiB)...
Write speed: 5MiB/s
Read speed: 6MiB/s
--============== Boot ==================--
Booting from serial...
Press Q or ESC to abort boot completely.
sL5DdSMmkekro
Timeout
No boot medium found
--============= Console ================--
litex> mem_list
Available memory regions:
ROM 0x00000000 0x6000
SRAM 0x01000000 0x1000
SPIFLASH 0x80000000 0x1000000
MAIN_RAM 0x40000000 0x800000
CSR 0x82000000 0x10000
litex> mem_test 0x40000000 0x800000
Memtest at 0x40000000 (8MiB)...
Write: 0x40000000-0x40800000 8MiB
Read: 0x40000000-0x40800000 8MiB
Memtest OK
litex>
91 lines
3.4 KiB
Python
91 lines
3.4 KiB
Python
#
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# This file is part of LiteX-Boards.
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#
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# Copyright (c) 2020 Pepijn de Vos <pepijndevos@gmail.com>
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# Copyright (c) 2021 Florent Kermarrec <florent@enjoy-digital.fr>
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# SPDX-License-Identifier: BSD-2-Clause
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from migen import *
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from litex.build.generic_platform import *
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from litex.build.gowin.platform import GowinPlatform
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from litex.build.openfpgaloader import OpenFPGALoader
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# IOs ----------------------------------------------------------------------------------------------
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_io = [
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# Clk / Rst
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("clk12", 0, Pins("35"), IOStandard("LVCMOS33")),
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("clk100", 0, Pins("63"), IOStandard("LVCMOS33")),
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("rst_n", 0, Pins("77"), IOStandard("LVCMOS33")),
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# Leds
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("user_led", 0, Pins("86"), IOStandard("LVCMOS33")),
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("user_led", 1, Pins("85"), IOStandard("LVCMOS33")),
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("user_led", 2, Pins("84"), IOStandard("LVCMOS33")),
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("user_led", 3, Pins("83"), IOStandard("LVCMOS33")),
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("user_led", 4, Pins("82"), IOStandard("LVCMOS33")),
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("user_led", 5, Pins("81"), IOStandard("LVCMOS33")),
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("user_led", 6, Pins("80"), IOStandard("LVCMOS33")),
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("user_led", 7, Pins("79"), IOStandard("LVCMOS33")),
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# Serial
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("serial", 0,
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Subsignal("tx", Pins("15"), IOStandard("LVCMOS33")),
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Subsignal("rx", Pins("16"), IOStandard("LVCMOS33")),
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),
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# SPIFlash
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("spiflash", 0,
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Subsignal("cs_n", Pins("51"), IOStandard("LVCMOS33")),
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Subsignal("clk", Pins("49"), IOStandard("LVCMOS33")),
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Subsignal("miso", Pins("53"), IOStandard("LVCMOS33")),
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Subsignal("mosi", Pins("48"), IOStandard("LVCMOS33")),
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Subsignal("wp", Pins("54"), IOStandard("LVCMOS33")),
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Subsignal("hold", Pins("50"), IOStandard("LVCMOS33")),
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),
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("spiflash4x", 0,
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Subsignal("cs_n", Pins("51")),
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Subsignal("clk", Pins("49")),
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Subsignal("dq", Pins("48 53 54 50")),
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IOStandard("LVCMOS33")
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),
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# SPIFlash (FTDI Chip)
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("spiflash", 1,
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Subsignal("cs_n", Pins("13"), IOStandard("LVCMOS33")),
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Subsignal("clk", Pins("16"), IOStandard("LVCMOS33")),
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Subsignal("miso", Pins("14"), IOStandard("LVCMOS33")),
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Subsignal("mosi", Pins("15"), IOStandard("LVCMOS33")),
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),
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# SDRAM (embedded in SIP, requires specific IO naming)
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("O_sdram_clk", 0, Pins(1), IOStandard("LVCMOS33")),
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("O_sdram_cke", 0, Pins(1), IOStandard("LVCMOS33")),
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("O_sdram_cs_n", 0, Pins(1), IOStandard("LVCMOS33")),
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("O_sdram_cas_n", 0, Pins(1), IOStandard("LVCMOS33")),
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("O_sdram_ras_n", 0, Pins(1), IOStandard("LVCMOS33")),
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("O_sdram_wen_n", 0, Pins(1), IOStandard("LVCMOS33")),
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("O_sdram_dqm", 0, Pins(2), IOStandard("LVCMOS33")),
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("O_sdram_addr", 0, Pins(12), IOStandard("LVCMOS33")),
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("O_sdram_ba", 0, Pins(2), IOStandard("LVCMOS33")),
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("IO_sdram_dq", 0, Pins(16), IOStandard("LVCMOS33")),
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]
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# Connectors ---------------------------------------------------------------------------------------
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_connectors = [
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("PMOD", "47 41 38 40 - - 36 42 39 37"),
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]
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# Platform -----------------------------------------------------------------------------------------
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class Platform(GowinPlatform):
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default_clk_name = "clk12"
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default_clk_period = 1e9/12e6
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def __init__(self):
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GowinPlatform.__init__(self, "GW1NR-LV9QN88C6/I5", _io, toolchain="gowin", devicename='GW1NR-9')
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def create_programmer(self):
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return OpenFPGALoader("littlebee")
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