Florent Kermarrec 7c48af9b50 tec0117: get SDRAM working and increase sys_clk_freq to 25MHz. ... ./tec0117.py --build --load Still some FIXMEs but validate use of the embedded SDRAM with LiteDRAM/LiteX: __ _ __ _ __ / / (_) /____ | |/_/ / /__/ / __/ -_)> < /____/_/\__/\__/_/|_| Build your hardware, easily! (c) Copyright 2012-2020 Enjoy-Digital (c) Copyright 2007-2015 M-Labs BIOS built on Feb 1 2021 13:09:35 BIOS CRC passed (5abceb2e) Migen git sha1: 40b1092 LiteX git sha1: f324f953 --=============== SoC ==================-- CPU: VexRiscv_Lite @ 25MHz BUS: WISHBONE 32-bit @ 4GiB CSR: 32-bit data ROM: 24KiB SRAM: 4KiB L2: 0KiB SDRAM: 8192KiB 16-bit @ 25MT/s (CL-2 CWL-2) --========== Initialization ============-- Initializing SDRAM @0x40000000... Switching SDRAM to software control. Switching SDRAM to hardware control. Memtest at 0x40000000 (2MiB)... Write: 0x40000000-0x40200000 2MiB Read: 0x40000000-0x40200000 2MiB Memtest OK Memspeed at 0x40000000 (2MiB)... Write speed: 5MiB/s Read speed: 6MiB/s --============== Boot ==================-- Booting from serial... Press Q or ESC to abort boot completely. sL5DdSMmkekro Timeout No boot medium found --============= Console ================-- litex> mem_list Available memory regions: ROM 0x00000000 0x6000 SRAM 0x01000000 0x1000 SPIFLASH 0x80000000 0x1000000 MAIN_RAM 0x40000000 0x800000 CSR 0x82000000 0x10000 litex> mem_test 0x40000000 0x800000 Memtest at 0x40000000 (8MiB)... Write: 0x40000000-0x40800000 8MiB Read: 0x40000000-0x40800000 8MiB Memtest OK litex>		2021-02-01 13:32:01 +01:00
..
platforms	tec0117: get SDRAM working and increase sys_clk_freq to 25MHz.	2021-02-01 13:32:01 +01:00
prog	Add FPC-III board support.	2021-01-28 09:51:42 -07:00
targets	tec0117: get SDRAM working and increase sys_clk_freq to 25MHz.	2021-02-01 13:32:01 +01:00
tools	general: add SPDX License identifier to header and specify files are part of LiteX-Boards.	2020-08-23 15:00:17 +02:00
__init__.py	init repo with litex official boards	2019-06-10 17:11:36 +02:00