Florent Kermarrec 7c48af9b50 tec0117: get SDRAM working and increase sys_clk_freq to 25MHz. ... ./tec0117.py --build --load Still some FIXMEs but validate use of the embedded SDRAM with LiteDRAM/LiteX: __ _ __ _ __ / / (_) /____ | |/_/ / /__/ / __/ -_)> < /____/_/\__/\__/_/|_| Build your hardware, easily! (c) Copyright 2012-2020 Enjoy-Digital (c) Copyright 2007-2015 M-Labs BIOS built on Feb 1 2021 13:09:35 BIOS CRC passed (5abceb2e) Migen git sha1: 40b1092 LiteX git sha1: f324f953 --=============== SoC ==================-- CPU: VexRiscv_Lite @ 25MHz BUS: WISHBONE 32-bit @ 4GiB CSR: 32-bit data ROM: 24KiB SRAM: 4KiB L2: 0KiB SDRAM: 8192KiB 16-bit @ 25MT/s (CL-2 CWL-2) --========== Initialization ============-- Initializing SDRAM @0x40000000... Switching SDRAM to software control. Switching SDRAM to hardware control. Memtest at 0x40000000 (2MiB)... Write: 0x40000000-0x40200000 2MiB Read: 0x40000000-0x40200000 2MiB Memtest OK Memspeed at 0x40000000 (2MiB)... Write speed: 5MiB/s Read speed: 6MiB/s --============== Boot ==================-- Booting from serial... Press Q or ESC to abort boot completely. sL5DdSMmkekro Timeout No boot medium found --============= Console ================-- litex> mem_list Available memory regions: ROM 0x00000000 0x6000 SRAM 0x01000000 0x1000 SPIFLASH 0x80000000 0x1000000 MAIN_RAM 0x40000000 0x800000 CSR 0x82000000 0x10000 litex> mem_test 0x40000000 0x800000 Memtest at 0x40000000 (8MiB)... Write: 0x40000000-0x40800000 8MiB Read: 0x40000000-0x40800000 8MiB Memtest OK litex>		2021-02-01 13:32:01 +01:00
..
__init__.py	Avoid Official/Partner/Community differentiation: use same directory for all platforms/targets.	2020-02-03 09:36:30 +01:00
ac701.py	targets/ac701: rename --ethernet-phy to --eth-phy for consistency with others targets.	2021-01-08 18:50:01 +01:00
acorn_cle_215.py	targets/xilinx: add comment on sys_clk to pll.clkin false path.	2021-01-07 08:01:54 +01:00
aller.py	targets/xilinx: add comment on sys_clk to pll.clkin false path.	2021-01-07 08:01:54 +01:00
alveo_u250.py	targets/xilinx: add comment on sys_clk to pll.clkin false path.	2021-01-07 08:01:54 +01:00
arrow_sockit.py	sockit: Fix cable name, default to jtag_atlantic	2021-02-01 11:48:06 +07:00
arty.py	add etherbone ip address option for relevant boards	2021-01-08 18:44:31 +01:00
arty_s7.py	targets/xilinx: add comment on sys_clk to pll.clkin false path.	2021-01-07 08:01:54 +01:00
c10lprefkit.py	targets/c10lprefkit: fix default sys-clk-freq.	2021-01-12 16:15:52 +01:00
camlink_4k.py	camlink_4k: disable leds when serial is used (since pin is shared).	2021-01-25 12:19:29 +01:00
colorlight_5a_75x.py	targets/colorlight_5a_75x: rename etherbone-ip args to eth-ip.	2021-01-07 09:26:38 +01:00
colorlight_i5.py	colorlight_i5: Use tx_delay=0 for LiteEthPHYRGMII instead of target specifig bios initialization	2021-01-27 18:19:27 +09:00
crosslink_nx_evn.py	nexus: Allow selection of toolchain	2020-11-25 09:45:25 +00:00
crosslink_nx_vip.py	nexus: Allow selection of toolchain	2020-11-25 09:45:25 +00:00
de0nano.py	targets/gensdrphy/halfsdrphy: pass new optional sys_clk_freq (used to compute cl).	2021-01-04 11:38:07 +01:00
de1soc.py	targets/gensdrphy/halfsdrphy: pass new optional sys_clk_freq (used to compute cl).	2021-01-04 11:38:07 +01:00
de2_115.py	targets/gensdrphy/halfsdrphy: pass new optional sys_clk_freq (used to compute cl).	2021-01-04 11:38:07 +01:00
de10lite.py	targets/gensdrphy/halfsdrphy: pass new optional sys_clk_freq (used to compute cl).	2021-01-04 11:38:07 +01:00
de10nano.py	targets/gensdrphy/halfsdrphy: pass new optional sys_clk_freq (used to compute cl).	2021-01-04 11:38:07 +01:00
ecp5_evn.py	targets: cleanup, uniformize build arguments between targets.	2020-11-12 11:46:00 +01:00
ecpix5.py	Add flash to SPI flash support for board ECPIX5 (needs update to openfpgaloader.py from litex to work)	2021-01-30 13:19:08 +01:00
fk33.py	targets/xilinx: add comment on sys_clk to pll.clkin false path.	2021-01-07 08:01:54 +01:00
fomu.py	targets/fomu: modification to ValentyUSB no longer required.	2020-11-27 19:40:45 +01:00
fpc_iii.py	targets/fpc_iii: review/cleanup to increase similarities with others targets to ease maintenance.	2021-01-29 08:46:31 +01:00
genesys2.py	Merge pull request #144 from gsomlo/gls-genesys2-sdcard	2021-01-07 08:12:24 +01:00
hadbadge.py	targets/gensdrphy/halfsdrphy: pass new optional sys_clk_freq (used to compute cl).	2021-01-04 11:38:07 +01:00
icebreaker.py	targets: add --sys-clk-freq support to all targets.	2020-11-12 18:07:28 +01:00
kc705.py	targets/xilinx: add comment on sys_clk to pll.clkin false path.	2021-01-07 08:01:54 +01:00
kcu105.py	add etherbone ip address option for relevant boards	2021-01-08 18:44:31 +01:00
kx2.py	targets/xilinx: add comment on sys_clk to pll.clkin false path.	2021-01-07 08:01:54 +01:00
linsn_rv901t.py	targets/gensdrphy/halfsdrphy: pass new optional sys_clk_freq (used to compute cl).	2021-01-04 11:38:07 +01:00
litefury.py	targets/xilinx: add comment on sys_clk to pll.clkin false path.	2021-01-07 08:01:54 +01:00
logicbone.py	target/usb_acm: switch git clone to litex-hub/valentyusb repo (up to date with LiteX).	2020-11-27 18:53:45 +01:00
mercury_xu5.py	targets/xilinx: add comment on sys_clk to pll.clkin false path.	2021-01-07 08:01:54 +01:00
mimas_a7.py	targets/xilinx: add comment on sys_clk to pll.clkin false path.	2021-01-07 08:01:54 +01:00
minispartan6.py	targets/xilinx: add comment on sys_clk to pll.clkin false path.	2021-01-07 08:01:54 +01:00
mist.py	targets/gensdrphy/halfsdrphy: pass new optional sys_clk_freq (used to compute cl).	2021-01-04 11:38:07 +01:00
nereid.py	targets/xilinx: add comment on sys_clk to pll.clkin false path.	2021-01-07 08:01:54 +01:00
netv2.py	netv2: add device variant to allow 100T as well	2021-01-28 13:19:53 +01:00
nexys4ddr.py	nexys4ddr: etherbone support	2021-01-15 12:14:40 -05:00
nexys_video.py	targets/xilinx: add comment on sys_clk to pll.clkin false path.	2021-01-07 08:01:54 +01:00
orangecrab.py	orangecrab: remove dm_remapping workaround: we are now using Wihsbone/L2 path with VexRiscv-SMP on this board.	2021-01-25 11:52:59 +01:00
pano_logic_g2.py	add etherbone ip address option for relevant boards	2021-01-08 18:44:31 +01:00
pipistrello.py	targets: add --sys-clk-freq support to all targets.	2020-11-12 18:07:28 +01:00
qmtech_ep4ce15.py	targets/gensdrphy/halfsdrphy: pass new optional sys_clk_freq (used to compute cl).	2021-01-04 11:38:07 +01:00
qmtech_wukong.py	add etherbone ip address option for relevant boards	2021-01-08 18:44:31 +01:00
redpitaya.py	targets/xilinx: add comment on sys_clk to pll.clkin false path.	2021-01-07 08:01:54 +01:00
sds1104xe.py	sds1104xe: defaults to Crossover UART.	2021-01-08 19:00:41 +01:00
simple.py	targets/simple: add try/except on leds.	2020-11-12 14:26:00 +01:00
tagus.py	targets/xilinx: add comment on sys_clk to pll.clkin false path.	2021-01-07 08:01:54 +01:00
tec0117.py	tec0117: get SDRAM working and increase sys_clk_freq to 25MHz.	2021-02-01 13:32:01 +01:00
tinyfpga_bx.py	targets: add --sys-clk-freq support to all targets.	2020-11-12 18:07:28 +01:00
trellisboard.py	targets: add --sys-clk-freq support to all targets.	2020-11-12 18:07:28 +01:00
ulx3s.py	ULX3S: Make spiflash optionally accessible from the SoC, and bootable	2021-01-23 14:44:26 -06:00
vc707.py	targets/xilinx: add comment on sys_clk to pll.clkin false path.	2021-01-07 08:01:54 +01:00
vcu118.py	targets/xilinx: add comment on sys_clk to pll.clkin false path.	2021-01-07 08:01:54 +01:00
versa_ecp5.py	add etherbone ip address option for relevant boards	2021-01-08 18:44:31 +01:00
xcu1525.py	targets/xilinx: add comment on sys_clk to pll.clkin false path.	2021-01-07 08:01:54 +01:00
zcu104.py	targets/xilinx: add comment on sys_clk to pll.clkin false path.	2021-01-07 08:01:54 +01:00
ztex213.py	Support file for the ZTEX USB-FPGA Module 2.13	2021-01-30 05:19:18 -05:00
zybo_z7.py	targets/xilinx: add comment on sys_clk to pll.clkin false path.	2021-01-07 08:01:54 +01:00