Florent Kermarrec
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fccb952c4b
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target: Remove ident_version=True no longer required.
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2022-01-18 17:13:02 +01:00 |
|
Florent Kermarrec
|
a4130556ac
|
gsd_butterstick: Add optional SYZYGY GPIO (--with-syzygy-gpio) to expose the 32 GPIOs on SYZYGY breakout board.
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2022-01-06 18:37:42 +01:00 |
|
Florent Kermarrec
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53dc00eab7
|
targets/parser: Rely on argparse.ArgumentDefaultsHelpFormatter to provide default in help description.
Also do minor adjustments while doing this.
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2022-01-05 17:06:40 +01:00 |
Greg Davill
|
fd2ec534a7
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butterstick: Add extra pins
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2021-12-05 20:33:28 +10:30 |
|
Greg Davill
|
c8a8e943b5
|
butterstick: add --sdram-device option
Set 64M16 as default sdram-device.
Related to #298
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2021-12-04 17:07:06 +10:30 |
|
Florent Kermarrec
|
91818bc5f0
|
targets/gsd_butterstick/BaseSoC: Set default device to 85F (consistency with default arguments).
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2021-10-26 17:01:55 +02:00 |
|
Florent Kermarrec
|
9e18d9bc34
|
gsd_butterstick: Remove ECLKBRIDGECS (not required).
|
2021-10-07 14:09:22 +02:00 |
|
Florent Kermarrec
|
68fb163a27
|
targets: Remove spiflash mapping on targets where it's no longer useful.
|
2021-09-14 18:35:13 +02:00 |
|
Florent Kermarrec
|
aa2209729f
|
gsd_butterstick: Force uart_name to crossover when set to serial.
|
2021-09-02 15:23:05 +02:00 |
|
Florent Kermarrec
|
fddca1cd40
|
gsd_butterstick: Add SDCard (SPI & SD modes) support.
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2021-09-02 14:06:09 +02:00 |
|
Florent Kermarrec
|
596f430326
|
gsd_butterstick: Add SPI Flash support.
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2021-09-02 11:28:21 +02:00 |
|
Florent Kermarrec
|
55ea71bd01
|
gsd_butterstick: Add initial DDR3 support.
Validated with:
./gsd_butterstick.py --uart-name=crossover --with-etherbone --csr-csv=csr.csv --build --load
litex_server --udp
litex_term bridge
__ _ __ _ __
/ / (_) /____ | |/_/
/ /__/ / __/ -_)> <
/____/_/\__/\__/_/|_|
Build your hardware, easily!
(c) Copyright 2012-2021 Enjoy-Digital
(c) Copyright 2007-2015 M-Labs
BIOS built on Sep 1 2021 19:09:52
BIOS CRC passed (3d349845)
Migen git sha1: 27dbf03
LiteX git sha1: 315fbe18
--=============== SoC ==================--
CPU: VexRiscv @ 75MHz
BUS: WISHBONE 32-bit @ 4GiB
CSR: 32-bit data
ROM: 128KiB
SRAM: 8KiB
L2: 8KiB
SDRAM: 524288KiB 16-bit @ 300MT/s (CL-6 CWL-5)
--========== Initialization ============--
Initializing SDRAM @0x40000000...
Switching SDRAM to software control.
Read leveling:
m0, b00: |01110000| delays: 02+-01
m0, b01: |00000000| delays: -
m0, b02: |00000000| delays: -
m0, b03: |00000000| delays: -
best: m0, b00 delays: 02+-01
m1, b00: |01110000| delays: 02+-01
m1, b01: |00000000| delays: -
m1, b02: |00000000| delays: -
m1, b03: |00000000| delays: -
best: m1, b00 delays: 02+-01
Switching SDRAM to hardware control.
Memtest at 0x40000000 (2.0MiB)...
Write: 0x40000000-0x40200000 2.0MiB
Read: 0x40000000-0x40200000 2.0MiB
Memtest OK
Memspeed at 0x40000000 (Sequential, 2.0MiB)...
Write speed: 13.6MiB/s
Read speed: 15.6MiB/s
--============== Boot ==================--
Booting from serial...
Press Q or ESC to abort boot completely.
sL5DdSMmkekro
Timeout
No boot medium found
--============= Console ================--
litex>
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2021-09-01 19:21:16 +02:00 |
|
Florent Kermarrec
|
1f25a98476
|
butterstick: Add Ethernet/Etherbone support (UART crossover working over Etherbone).
|
2021-09-01 18:03:13 +02:00 |
|
Florent Kermarrec
|
1f149ece6b
|
Add intial ButterStick support (with just Clk, Buttons and Leds).
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2021-09-01 17:33:54 +02:00 |