Commit Graph

6 Commits

Author SHA1 Message Date
Florent Kermarrec 74a5ffb9ef targets/Ultrascale+: use 500MHz IDELAYCTRL reference clock.
The minimum is 300MHz on Ultrascale+ vs 200MHz on Ultrascale.
2020-03-10 16:58:30 +01:00
Florent Kermarrec e2a66090ee targets/Ultrascale(+): simplify CRG using USIDELAYCTRL. 2020-03-10 16:55:22 +01:00
Florent Kermarrec cf58550bba targets/Ultrascale+: use USPDDRPHY. 2020-03-10 16:06:48 +01:00
Florent Kermarrec f279fe9d33 vc707: cleanup platform/targets, remove Ethernet support (no Ethernet pads defined) 2020-02-25 10:35:18 +01:00
Florent Kermarrec 88a1f80db1 vc707/vcu118: use proper copyrights 2020-02-25 09:03:52 +01:00
Fei Gao 373e74f435 add new board files for VC707 and VCU118, only specified limited ports for VCU118, including clock, reset and DDR4 2020-02-24 14:20:47 -05:00