Hardware
/
litex-boards
mirror of https://github.com/litex-hub/litex-boards.git
1
0
Fork 0
Code Issues Packages Projects Releases Wiki Activity
1,652 Commits 9 Branches 14 Tags 11 MiB
Commit Graph

8 Commits

Author SHA1 Message Date
Florent Kermarrec 45494f60e0 targets: Change SoC/Software headers generation behaviour (Now only generated with --build). 
Re-generating the SoC/Software headers was causing some un-expected behaviours for users not familiar
with the flow. For example doing a --load with a different configuration, was re-generating the Software
headers and messing up things when trying to run software on the SoC.
 2022-05-06 15:14:32 +02:00
Florent Kermarrec 877bc4b45e targets: Use full imports (vendor_board). 2022-05-02 12:55:11 +02:00
Florent Kermarrec a611f035d6 targets: Move CRG before SoCCore init (More logical and simplify some specific reset schemes) and switch SoCCore to one line when possible. 
Moving CRG simplify reset with NaxRiscv debug module and is in fact more logical.
Also do some minor updates/cosmetic changes while touching CRG/SoCCore.
 2022-04-21 12:19:45 +02:00
Florent Kermarrec b2a346edc8 aliexpress_u420t: Review/Simplify. 
Specific integrated ROM/SRAM/MAIN_RAM size can be passed through command line parameters.
 2022-04-21 10:32:18 +02:00
Florent Kermarrec 9d452b0d74 targets: Create target_group for target arguments. 2022-03-21 18:37:40 +01:00
Florent Kermarrec cc8da9d341 targets: Simplify imports and switch to LiteXSocArgumentParser. 
CPU parameters are now selectively exposed to the user:
./digilent_arty.py --cpu-type=vexriscv_smp --help will show VexRiscv-SMP parameters.
./digilent_arty.py --cpu-type=naxriscv --help will show NaxRiscv parameters.
 2022-03-21 16:59:40 +01:00
Florent Kermarrec 9faa805ab9 alinx_ax7010: Review/Cleanup. 2022-03-17 11:31:02 +01:00
Yonggang Liu 94786cae19
Update and rename xilinx_alinx_ax7010.py to alinx_ax7010.py 2022-03-17 11:24:24 +08:00