1b676f929a
cleanup and ease of use
...
- update README
- delete some unnecessary toolchain commands (copied from trenz boards)
- use minimal cpu_variant by default when vexriscv is selected
2021-10-03 13:21:45 -04:00
4a52996106
Wukong board improvements
...
This adds support for v2 of the board via a --board-version argument
and a way to select the FPGA speed grade via a --speed-grade argument.
Note that the speed grade now defaults to -1. QMTech confirmed that
V1 of the board were made in two batches, one with -1 and one with -2,
while V2 of the board is all -1. So -1 is the safer default.
This also fixes the inversion of j10 and j11 and a typo in the pin
definition of jp3
Signed-off-by: Benjamin Herrenschmidt <benh@kernel.crashing.org>
2021-09-24 12:13:56 +10:00
610e82d774
Add initial RZ-EasyFPGA support! ( #270 )
2021-09-21 09:55:22 +02:00
b75af2f21c
Update README.md
...
FPGA on "Zybo Z7" is a 7-Series Zynq not a Zynq Ultrascale+
2021-09-15 10:21:10 -04:00
781d83bab6
Add support for EBAZ4205 'Development' Board
...
Usage:
```
./ebaz4205.py --cpu-type=vexriscv --build --load
```
```
$ pwd
litex-boards/litex_boards/targets
```
Tip: Use `GTKTerm` to connect to /dev/ttyUSB0 (usually) and interact
with the LiteX BIOS.
References:
- https://github.com/fusesoc/blinky#ebaz4205-development-board
- https://github.com/olofk/serv/#ebaz4205-development-board
- https://github.com/xjtuecho/EBAZ4205#ebaz4205
- https://github.com/nmigen/nmigen-boards/pull/180 (merged)
- https://github.com/olofk/corescore/pull/33
- The existing 'Zybo Z7' example
Note: The `PS7` stuff remains untested via LiteX for now.
2021-08-31 18:54:49 +02:00
126c98488a
update IRC channel
2021-08-16 14:18:08 -04:00
25867c4dcb
Merge pull request #218 from helium729/master
...
Add digilent basys3 board support
2021-05-23 19:46:58 +02:00
dd5a4bdc92
CYC1000: Add initial support of CYC1000 board
2021-05-22 21:17:27 +02:00
95b589fc22
add info to README
2021-05-17 16:49:04 +08:00
5ae130661f
Merge pull request #213 from hansfbaier/icesugar
...
muselab_icesugar: first basic version which boots
2021-05-07 08:50:50 +02:00
c2e0f6026e
muselab_icesugar: first basic version that boots
2021-05-07 11:50:28 +07:00
eec1078736
add QMTECH XC7A35T core board + daughter board
2021-05-06 05:50:48 +07:00
9e42183066
update AU280 description
2021-04-27 17:29:55 -04:00
f4ea3fb0d9
Merge pull request #168 from hplp/alveo_u280
...
Alveo U280 board
2021-03-10 11:16:32 +01:00
767e2875b3
README.md: fix typo
2021-02-26 04:55:11 +07:00
6f558a5d65
Add board support for Terasic/Arrow DECA board
2021-02-25 12:25:43 +07:00
bc255a6a0d
arrow_sockit: Add README table entry and test target
2021-02-25 12:25:43 +07:00
5a1447dc5c
mention HBM2
2021-01-15 17:52:17 -05:00
58e25757eb
list Alveo U280
2021-01-15 12:16:10 -05:00
e1f9fd1a25
README: update and center banner.
2020-12-17 18:55:13 +01:00
b9d9af3183
ci: switch from Travis CI to Github Actions.
2020-11-24 14:01:23 +01:00
389b623fe2
targets/litefury: new target
...
LiteFury is an Artix-7 development board in the M.2 form factor
for PCIe accelerator development. It's similar to the Aller but
with an xc7a100t rather than an xc7a200t and no TPM module.
https://rhsresearch.com/collections/rhs-public/products/litefury
2020-11-19 21:52:14 -08:00
27f60b2e93
add initial Siglent SDS1104X-E support (Ethernet & DDR3 validated).
...
Pinout from https://github.com/360nosc0pe project.
2020-11-13 12:20:15 +01:00
f0581815f5
README: fix typo.
2020-07-28 17:44:30 +02:00
ecdc1ef7fd
README: add missings .
2020-07-27 11:44:30 +02:00
361afa74b6
README: add links to LiteX's wiki.
2020-07-27 11:05:14 +02:00
02c0c0a1b1
README: add board picture and fix a few typos.
2020-07-27 08:53:12 +02:00
bfbee484c7
Readme/boards: fill most of the missing infos.
2020-07-25 22:17:22 +02:00
e9706d4465
README: add initial contents and list of supported boards.
2020-07-25 20:21:51 +02:00
alainlou
Benjamin Herrenschmidt
Kamyar Mohajerani
Dhiru Kholia
enjoy-digital
Jakub Cabal
helium729
Hans Baier
Sergiu Mosanu
Nathaniel R. Lewis