3 Commits

Author	SHA1	Message	Date
alainlou	1b676f929a	cleanup and ease of use ... - update README - delete some unnecessary toolchain commands (copied from trenz boards) - use minimal cpu_variant by default when vexriscv is selected	2021-10-03 13:21:45 -04:00
alainlou	1333f89ed6	rz_easyfpga: adjust SDRAM clk phase ... - also add 1:2 rate	2021-09-22 00:26:28 -04:00
Alain Lou	610e82d774	Add initial RZ-EasyFPGA support! (#270)	2021-09-21 09:55:22 +02:00