Florent Kermarrec
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0ce7f8354c
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Add initial LimeSDR Mini V2 support (With SoC + USB3 (FT245PHYSynchronous)).
python3 -m litex_boards.targets.limesdr_mini_v2 --csr-csv=csr.csv --build --load
litex_server --jtag --jtag-config=openocd_limesdr_mini_v2.cfg
litex_term crossover
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Build your hardware, easily!
(c) Copyright 2012-2022 Enjoy-Digital
(c) Copyright 2007-2015 M-Labs
BIOS built on May 3 2022 18:59:46
BIOS CRC passed (5f29afcc)
LiteX git sha1: a4cc859d
--=============== SoC ==================--
CPU: VexRiscv @ 80MHz
BUS: WISHBONE 32-bit @ 4GiB
CSR: 32-bit data
ROM: 128KiB
SRAM: 8KiB
--============== Boot ==================--
Booting from serial...
Press Q or ESC to abort boot completely.
sL5DdSMmkekro
Timeout
No boot medium found
--============= Console ================--
litex> ident
Ident: LiteX SoC on LimeSDR-Mini-V2 2022-05-03 18:59:29
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2022-05-03 19:04:06 +02:00 |
Gwenhael Goavec-Merou