842819d832
platforms/xilinx_zcu102: Add pin definitions for DDR4 SDRAM and FMC connectors.
2023-10-13 23:53:10 +09:00
6f0cd56109
update to match zcu102 constraint spec
2023-09-28 11:11:21 +02:00
5f8ac853b1
Resolve High Density bank IOStandard error
...
This resolves the following error during `build` on Vivado 2023.1:
```ERROR: [DRC BIVB-1] Bank IO standard Support: Bank 47 has incompatible IO(s) because: The LVDS I/O standard is not supported for banks of type High Density. Move the following ports or change their properties:
clk125_p```
2023-09-25 12:50:30 +02:00
47659835b0
platforms: Switch US/USP platforms to XilinxUS/USPPlatform.
...
We were still using Xilinx7SeriesPlatform.
2023-03-01 09:37:55 +01:00
9960f38d95
targets: replace LiteXSoCArgumentParser by LiteXArgumentParser, remove tasks done LiteXArgumentParser
2022-11-06 11:27:47 +01:00
0745162a29
xilinx_zcu102: Review/Cleanup for consistency with others boards.
...
Also remove INTERNAL_VREF constraints that are not yet useful (required for DRAM).
2022-03-16 18:47:05 +01:00
f4a48e51d7
add xilinx_zcu102 platform
2022-03-16 15:37:02 +01:00
rniwase
Liana Koleva
Florent Kermarrec
Gwenhael Goavec-Merou
Joseph Faye