Florent Kermarrec
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fccb952c4b
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target: Remove ident_version=True no longer required.
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2022-01-18 17:13:02 +01:00 |
|
Florent Kermarrec
|
4b6a9b2cf0
|
targets/spiflash: Simplify self.cpu.set_reset_address call.
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2022-01-07 15:19:23 +01:00 |
|
Florent Kermarrec
|
8151bf7ffa
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targets: Update and simplify SPI-Flash support (Address is now automatically allocated).
|
2022-01-07 10:34:47 +01:00 |
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Florent Kermarrec
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53dc00eab7
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targets/parser: Rely on argparse.ArgumentDefaultsHelpFormatter to provide default in help description.
Also do minor adjustments while doing this.
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2022-01-05 17:06:40 +01:00 |
Ilia Sergachev
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14a8c50e97
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sipeed_tang_nano_4k: connect Gowin EMCU UART, undo unnecessary changes
|
2021-12-09 00:17:48 +01:00 |
|
Ilia Sergachev
|
6274c4c425
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sipeed_tang_nano_4k: connect Gowin EMCU UART
|
2021-12-09 00:12:31 +01:00 |
|
Ilia Sergachev
|
13c83ba532
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sipeed_tang_nano_4k: add initial Gowin EMCU support
|
2021-12-08 23:50:14 +01:00 |
|
Ilia Sergachev
|
4287ab561e
|
sipeed_tang_nano_4k: allow non-vexriscv CPUs
|
2021-12-08 23:33:49 +01:00 |
|
Ilia Sergachev
|
666ef9dad3
|
sipeed_tang_nano_4k: use minimal vexriscv variant to fit into number of BSRAMs
|
2021-11-29 11:46:32 +01:00 |
|
Ilia Sergachev
|
2fb734a0f2
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sipeed_tang_nano*: adapt Gowin PLL changes in litex
|
2021-11-29 11:45:13 +01:00 |
|
Florent Kermarrec
|
5190c9c869
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sipeed_tang_nano_4k: Initial Video Out support.
With colorbars for now, need to free up BRAMS for Video Terminal (or finish HyperRAM support).
|
2021-09-20 09:32:20 +02:00 |
|
Florent Kermarrec
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7161ad18ec
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sipeed_tang_nano_4k: Integrate new LiteX's GW1NSRPLL.
|
2021-09-20 08:40:19 +02:00 |
|
Florent Kermarrec
|
a5c5ba7652
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sipeed_tang_nano_4k: Integrate HyperRam (not yet working).
|
2021-09-17 16:30:39 +02:00 |
|
Florent Kermarrec
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376a836583
|
sipeed_tang_nano: Add SPI Flash, Enable CPU and use new external SPI Flash support from OpenFPGALoader.
./sipeed_tang_nano_4k.py --cpu-type=vexriscv --cpu-variant=lite --build --flash
__ _ __ _ __
/ / (_) /____ | |/_/
/ /__/ / __/ -_)> <
/____/_/\__/\__/_/|_|
Build your hardware, easily!
(c) Copyright 2012-2021 Enjoy-Digital
(c) Copyright 2007-2015 M-Labs
BIOS built on Sep 17 2021 15:54:08
BIOS CRC passed (6cc6de6d)
Migen git sha1: a5bc262
LiteX git sha1: 46cd9c5a
--=============== SoC ==================--
CPU: VexRiscv_Lite @ 27MHz
BUS: WISHBONE 32-bit @ 4GiB
CSR: 32-bit data
ROM: 64KiB
SRAM: 8KiB
FLASH: 4096KiB
--========== Initialization ============--
Initializing W25Q32 SPI Flash @0x80000000...
SPI Flash clk configured to 13 MHz
Memspeed at 0x80000000 (Sequential, 4.0KiB)...
Read speed: 1.3MiB/s
Memspeed at 0x80000000 (Random, 4.0KiB)...
Read speed: 521.9KiB/s
--============== Boot ==================--
Booting from serial...
Press Q or ESC to abort boot completely.
sL5DdSMmkekro
Timeout
No boot medium found
--============= Console ================--
litex>
|
2021-09-17 15:57:55 +02:00 |
|
Florent Kermarrec
|
5955a35372
|
Add initial Sipeed Tang Nano support (Clk/Leds/Buttons).
|
2021-09-16 19:22:30 +02:00 |
|
Florent Kermarrec
|
8d91489756
|
tang_nano_4k: Add more IOs.
|
2021-09-09 11:23:20 +02:00 |
|
Florent Kermarrec
|
88534c6689
|
tang_nano_4k: Fix typo in sipeed.
|
2021-09-08 23:02:39 +02:00 |