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1,637 Commits 9 Branches 14 Tags 11 MiB
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14 Commits

Author SHA1 Message Date
Florent Kermarrec 45494f60e0 targets: Change SoC/Software headers generation behaviour (Now only generated with --build). 
Re-generating the SoC/Software headers was causing some un-expected behaviours for users not familiar
with the flow. For example doing a --load with a different configuration, was re-generating the Software
headers and messing up things when trying to run software on the SoC.
 2022-05-06 15:14:32 +02:00
Florent Kermarrec 877bc4b45e targets: Use full imports (vendor_board). 2022-05-02 12:55:11 +02:00
Florent Kermarrec 88f2625c3d targets: Fix typos. 2022-04-21 12:29:54 +02:00
Florent Kermarrec a611f035d6 targets: Move CRG before SoCCore init (More logical and simplify some specific reset schemes) and switch SoCCore to one line when possible. 
Moving CRG simplify reset with NaxRiscv debug module and is in fact more logical.
Also do some minor updates/cosmetic changes while touching CRG/SoCCore.
 2022-04-21 12:19:45 +02:00
Florent Kermarrec 9d452b0d74 targets: Create target_group for target arguments. 2022-03-21 18:37:40 +01:00
Florent Kermarrec cc8da9d341 targets: Simplify imports and switch to LiteXSocArgumentParser. 
CPU parameters are now selectively exposed to the user:
./digilent_arty.py --cpu-type=vexriscv_smp --help will show VexRiscv-SMP parameters.
./digilent_arty.py --cpu-type=naxriscv --help will show NaxRiscv parameters.
 2022-03-21 16:59:40 +01:00
Florent Kermarrec 496b2cfab9 targets/gowin: Switch to get_bitstream_filename. 2022-03-17 09:40:10 +01:00
Florent Kermarrec 773444a7dd targets: Switch to get_bios_filename/get_bitstream_filename. 2022-03-17 09:21:05 +01:00
Florent Kermarrec fccb952c4b target: Remove ident_version=True no longer required. 2022-01-18 17:13:02 +01:00
Florent Kermarrec 53dc00eab7 targets/parser: Rely on argparse.ArgumentDefaultsHelpFormatter to provide default in help description. 
Also do minor adjustments while doing this.
 2022-01-05 17:06:40 +01:00
Ilia Sergachev 2fb734a0f2 sipeed_tang_nano*: adapt Gowin PLL changes in litex 2021-11-29 11:45:13 +01:00
Florent Kermarrec 184f41e61a sipeed_tang_nano: Use PLL and 48MHz sys_clk, switch to SoCMini, add UARTBone (at 1MBauds). 
Working correctly on hardware with updated CH552 firmware & patched litex_server...
 2021-11-08 09:23:44 +01:00
Florent Kermarrec 28571308bc sispeed_tang_nano: Add simple UART loopback test... (Not working...) 2021-09-16 19:34:48 +02:00
Florent Kermarrec 5955a35372 Add initial Sipeed Tang Nano support (Clk/Leds/Buttons). 2021-09-16 19:22:30 +02:00