186 lines
8.6 KiB
Python
Executable File
186 lines
8.6 KiB
Python
Executable File
#!/usr/bin/env python3
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#
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# This file is part of LiteX-Boards.
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#
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# Copyright (c) 2021 Hans Baier <hansfbaier@gmail.com>
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# SPDX-License-Identifier: BSD-2-Clause
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import os
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import argparse
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from migen import *
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from migen.genlib.resetsync import AsyncResetSynchronizer
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from litex.build.io import DDROutput
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from litex_boards.platforms import qmtech_10cl006
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from litex.soc.cores.clock import Cyclone10LPPLL
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from litex.soc.integration.soc_core import *
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from litex.soc.integration.builder import *
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from litex.soc.cores.led import LedChaser
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from litedram.modules import W9825G6KH6
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from litedram.phy import GENSDRPHY, HalfRateGENSDRPHY
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from litex.soc.cores.video import VideoVGAPHY
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from liteeth.phy.mii import LiteEthPHYMII
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# CRG ----------------------------------------------------------------------------------------------
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class _CRG(Module):
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def __init__(self, platform, sys_clk_freq, with_ethernet, with_vga, sdram_rate="1:1"):
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self.rst = Signal()
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self.clock_domains.cd_sys = ClockDomain()
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if sdram_rate == "1:2":
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self.clock_domains.cd_sys2x = ClockDomain()
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self.clock_domains.cd_sys2x_ps = ClockDomain(reset_less=True)
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else:
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self.clock_domains.cd_sys_ps = ClockDomain(reset_less=True)
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if with_ethernet:
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self.clock_domains.cd_eth = ClockDomain()
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if with_vga:
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self.clock_domains.cd_vga = ClockDomain(reset_less=True)
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# # #
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# Clk / Rst
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clk50 = platform.request("clk50")
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# PLL
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self.submodules.pll = pll = Cyclone10LPPLL(speedgrade="-C8")
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self.comb += pll.reset.eq(self.rst)
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pll.register_clkin(clk50, 50e6)
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pll.create_clkout(self.cd_sys, sys_clk_freq)
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if sdram_rate == "1:2":
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pll.create_clkout(self.cd_sys2x, 2*sys_clk_freq)
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# theoretically 90 degrees, but increase to relax timing
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pll.create_clkout(self.cd_sys2x_ps, 2*sys_clk_freq, phase=180)
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else:
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pll.create_clkout(self.cd_sys_ps, sys_clk_freq, phase=90)
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if with_ethernet:
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pll.create_clkout(self.cd_eth, 25e6)
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if with_vga:
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pll.create_clkout(self.cd_vga, 40e6)
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# SDRAM clock
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sdram_clk = ClockSignal("sys2x_ps" if sdram_rate == "1:2" else "sys_ps")
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self.specials += DDROutput(1, 0, platform.request("sdram_clock"), sdram_clk)
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# BaseSoC ------------------------------------------------------------------------------------------
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class BaseSoC(SoCCore):
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def __init__(self, sys_clk_freq=int(50e6), with_daughterboard=False,
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with_ethernet=False, with_etherbone=False, eth_ip="192.168.1.50", eth_dynamic_ip=False,
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with_led_chaser=True, with_video_terminal=False, with_video_framebuffer=False,
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ident_version=True, sdram_rate="1:1", **kwargs):
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platform = qmtech_10cl006.Platform(with_daughterboard=with_daughterboard)
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# SoCCore ----------------------------------------------------------------------------------
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SoCCore.__init__(self, platform, sys_clk_freq,
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ident = "LiteX SoC on QMTECH 10CL006" + (" + Daughterboard" if with_daughterboard else ""),
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ident_version = ident_version,
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**kwargs)
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# CRG --------------------------------------------------------------------------------------
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self.submodules.crg = _CRG(platform,
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sys_clk_freq, with_ethernet or with_etherbone,
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with_video_terminal or with_video_framebuffer,
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sdram_rate=sdram_rate)
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# SDR SDRAM --------------------------------------------------------------------------------
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if not self.integrated_main_ram_size:
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sdrphy_cls = HalfRateGENSDRPHY if sdram_rate == "1:2" else GENSDRPHY
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self.submodules.sdrphy = sdrphy_cls(platform.request("sdram"), sys_clk_freq)
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self.add_sdram("sdram",
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phy = self.sdrphy,
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module = W9825G6KH6(sys_clk_freq, sdram_rate),
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l2_cache_size = kwargs.get("l2_size", 8192)
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)
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# Ethernet / Etherbone ---------------------------------------------------------------------
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if with_ethernet or with_etherbone:
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self.submodules.ethphy = LiteEthPHYMII(
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clock_pads = self.platform.request("eth_clocks"),
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pads = self.platform.request("eth"))
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if with_ethernet:
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self.add_ethernet(phy=self.ethphy, dynamic_ip=eth_dynamic_ip)
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if with_etherbone:
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self.add_etherbone(phy=self.ethphy, ip_address=eth_ip)
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# Video ------------------------------------------------------------------------------------
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if with_video_terminal or with_video_framebuffer:
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self.submodules.videophy = VideoVGAPHY(platform.request("vga"), clock_domain="vga")
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if with_video_terminal:
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self.add_video_terminal(phy=self.videophy, timings="800x600@60Hz", clock_domain="vga")
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if with_video_framebuffer:
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self.add_video_framebuffer(phy=self.videophy, timings="800x600@60Hz", clock_domain="vga")
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# Leds -------------------------------------------------------------------------------------
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if with_led_chaser:
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self.submodules.leds = LedChaser(
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pads = platform.request_all("user_led"),
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sys_clk_freq = sys_clk_freq)
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# Build --------------------------------------------------------------------------------------------
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def main():
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parser = argparse.ArgumentParser(description="LiteX SoC on QMTECH 10CL006")
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parser.add_argument("--build", action="store_true", help="Build bitstream")
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parser.add_argument("--load", action="store_true", help="Load bitstream")
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parser.add_argument("--sys-clk-freq", default=50e6, help="System clock frequency (default: 50MHz)")
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parser.add_argument("--sdram-rate", default="1:1", help="SDRAM Rate: 1:1 Full Rate (default) or 1:2 Half Rate")
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parser.add_argument("--with-daughterboard", action="store_true", help="Whether the core board is plugged into the QMTech daughterboard")
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ethopts = parser.add_mutually_exclusive_group()
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ethopts.add_argument("--with-ethernet", action="store_true", help="Enable Ethernet support")
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ethopts.add_argument("--with-etherbone", action="store_true", help="Enable Etherbone support")
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parser.add_argument("--eth-ip", default="192.168.1.50", type=str, help="Ethernet/Etherbone IP address")
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parser.add_argument("--eth-dynamic-ip", action="store_true", help="Enable dynamic Ethernet IP addresses setting")
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sdopts = parser.add_mutually_exclusive_group()
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sdopts.add_argument("--with-spi-sdcard", action="store_true", help="Enable SPI-mode SDCard support")
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sdopts.add_argument("--with-sdcard", action="store_true", help="Enable SDCard support")
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parser.add_argument("--with-spi-flash", action="store_true", help="Enable SPI Flash (MMAPed)")
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parser.add_argument("--no-ident-version", action="store_false", help="Disable build time output")
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viopts = parser.add_mutually_exclusive_group()
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viopts.add_argument("--with-video-terminal", action="store_true", help="Enable Video Terminal (VGA)")
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viopts.add_argument("--with-video-framebuffer", action="store_true", help="Enable Video Framebuffer (VGA)")
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builder_args(parser)
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soc_core_args(parser)
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args = parser.parse_args()
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soc = BaseSoC(
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sys_clk_freq = int(float(args.sys_clk_freq)),
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with_daughterboard = args.with_daughterboard,
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with_ethernet = args.with_ethernet,
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with_etherbone = args.with_etherbone,
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eth_ip = args.eth_ip,
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eth_dynamic_ip = args.eth_dynamic_ip,
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ident_version = args.no_ident_version,
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with_video_terminal = args.with_video_terminal,
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with_video_framebuffer = args.with_video_framebuffer,
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with_spi_flash = args.with_spi_flash,
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sdram_rate = args.sdram_rate,
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**soc_core_argdict(args)
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)
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if args.with_spi_sdcard:
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soc.add_spi_sdcard()
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if args.with_sdcard:
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soc.add_sdcard()
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builder = Builder(soc, **builder_argdict(args))
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builder.build(run=args.build)
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if args.load:
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prog = soc.platform.create_programmer()
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prog.load_bitstream(os.path.join(builder.gateware_dir, soc.build_name + ".sof"))
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if __name__ == "__main__":
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main()
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