litex-boards/litex_boards/partner/targets
Florent Kermarrec 2ec6bc0bdc colorlight_5a_75b: add disclaimer 2020-01-23 14:13:13 +01:00
..
__init__.py import: allow importing directly from litex_boards.platforms or litex_boards.targets 2019-09-03 15:30:20 +02:00
aller.py aller/nereid/tagus: update litepcie 2020-01-21 21:26:23 +01:00
c10lprefkit.py targets: cleanup EthernetSoC 2020-01-16 10:28:09 +01:00
camlink_4k.py targets: use default integrated rom/ram size passed with **kwargs from default soc_core_args 2020-01-13 15:20:37 +01:00
colorlight_5a_75b.py colorlight_5a_75b: add disclaimer 2020-01-23 14:13:13 +01:00
fomu.py travis: update/fix 2020-01-13 17:00:01 +01:00
hadbadge.py targets: use default integrated rom/ram size passed with **kwargs from default soc_core_args 2020-01-13 15:20:37 +01:00
linsn_rv901t.py targets/linsn_rv901t: cleanup arguments 2020-01-22 09:04:28 +01:00
nereid.py aller/nereid/tagus: update litepcie 2020-01-21 21:26:23 +01:00
netv2.py targets: cleanup EthernetSoC 2020-01-16 10:28:09 +01:00
orangecrab.py targets: use default integrated rom/ram size passed with **kwargs from default soc_core_args 2020-01-13 15:20:37 +01:00
tagus.py aller/nereid/tagus: update litepcie 2020-01-21 21:26:23 +01:00
trellisboard.py targets: cleanup EthernetSoC 2020-01-16 10:28:09 +01:00
ulx3s.py targets: use default integrated rom/ram size passed with **kwargs from default soc_core_args 2020-01-13 15:20:37 +01:00