96 lines
3.8 KiB
Python
Executable File
96 lines
3.8 KiB
Python
Executable File
#!/usr/bin/env python3
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# This file is Copyright (c) 2018-2019 Florent Kermarrec <florent@enjoy-digital.fr>
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# This file is Copyright (c) 2018 David Shah <dave@ds0.me>
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# License: BSD
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import argparse
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import sys
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from migen import *
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from migen.genlib.resetsync import AsyncResetSynchronizer
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from litex_boards.platforms import ulx3s
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from litex.soc.cores.clock import *
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from litex.soc.integration.soc_sdram import *
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from litex.soc.integration.builder import *
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from litedram import modules as litedram_modules
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from litedram.phy import GENSDRPHY
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# CRG ----------------------------------------------------------------------------------------------
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class _CRG(Module):
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def __init__(self, platform, sys_clk_freq):
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self.clock_domains.cd_sys = ClockDomain()
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self.clock_domains.cd_sys_ps = ClockDomain(reset_less=True)
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# # #
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# Clk / Rst
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clk25 = platform.request("clk25")
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rst = platform.request("rst")
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platform.add_period_constraint(clk25, 1e9/25e6)
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# PLL
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self.submodules.pll = pll = ECP5PLL()
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self.comb += pll.reset.eq(rst)
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pll.register_clkin(clk25, 25e6)
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pll.create_clkout(self.cd_sys, sys_clk_freq, phase=11)
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pll.create_clkout(self.cd_sys_ps, sys_clk_freq, phase=20)
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self.specials += AsyncResetSynchronizer(self.cd_sys, ~pll.locked | rst)
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# SDRAM clock
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self.comb += platform.request("sdram_clock").eq(self.cd_sys_ps.clk)
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# Prevent ESP32 from resetting FPGA
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self.comb += platform.request("wifi_gpio0").eq(1)
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# BaseSoC ------------------------------------------------------------------------------------------
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class BaseSoC(SoCSDRAM):
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def __init__(self, device="LFE5U-45F", toolchain="diamond",
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sys_clk_freq=int(50e6), sdram_module_cls="MT48LC16M16", **kwargs):
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platform = ulx3s.Platform(device=device, toolchain=toolchain)
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# SoCSDRAM ---------------------------------------------------------------------------------
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SoCSDRAM.__init__(self, platform, clk_freq=sys_clk_freq, **kwargs)
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# CRG --------------------------------------------------------------------------------------
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self.submodules.crg = _CRG(platform, sys_clk_freq)
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# SDR SDRAM --------------------------------------------------------------------------------
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if not self.integrated_main_ram_size:
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self.submodules.sdrphy = GENSDRPHY(platform.request("sdram"), cl=2)
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sdram_module = getattr(litedram_modules, sdram_module_cls)(sys_clk_freq, "1:1")
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self.register_sdram(self.sdrphy,
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sdram_module.geom_settings,
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sdram_module.timing_settings)
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# Build --------------------------------------------------------------------------------------------
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def main():
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parser = argparse.ArgumentParser(description="LiteX SoC on ULX3S")
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parser.add_argument("--gateware-toolchain", dest="toolchain", default="diamond",
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help='gateware toolchain to use, diamond (default) or trellis')
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parser.add_argument("--device", dest="device", default="LFE5U-45F",
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help='FPGA device, ULX3S can be populated with LFE5U-45F (default) or LFE5U-85F')
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parser.add_argument("--sys-clk-freq", default=50e6,
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help="system clock frequency (default=50MHz)")
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parser.add_argument("--sdram-module", default="MT48LC16M16",
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help="SDRAM module: MT48LC16M16, AS4C32M16 or AS4C16M16 (default=MT48LC16M16)")
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builder_args(parser)
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soc_sdram_args(parser)
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args = parser.parse_args()
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soc = BaseSoC(device=args.device, toolchain=args.toolchain,
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sys_clk_freq=int(float(args.sys_clk_freq)),
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sdram_module_cls=args.sdram_module,
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**soc_sdram_argdict(args))
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builder = Builder(soc, **builder_argdict(args))
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builder.build()
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if __name__ == "__main__":
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main()
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