Sergiu Mosanu 1916677dc9 use VREF constraint for DDR4 C0		2021-01-28 19:58:38 -05:00
..
platforms	use VREF constraint for DDR4 C0	2021-01-28 19:58:38 -05:00
prog	colorlight_5a_75x: switch prog to FT232 based programmer (ex: JTAG HS2).	2020-11-23 10:13:57 +01:00
targets	re-compare and adjust to u250	2021-01-26 23:03:09 -05:00
tools	general: add SPDX License identifier to header and specify files are part of LiteX-Boards.	2020-08-23 15:00:17 +02:00
__init__.py	init repo with litex official boards	2019-06-10 17:11:36 +02:00