Florent Kermarrec 1ac1c6857f targets/xilinx: add false path constraint between sys_clk and pll.clkin. ... The SoC reset added recently creates a path between sys_clk and pll.clkin clock domains that is reported by the tools but that can be safely ignored.		2021-01-07 00:02:46 +01:00
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platforms	platforms/colorlight_5a_75b: revert toolchain args.	2020-12-29 14:22:42 +01:00
prog	colorlight_5a_75x: switch prog to FT232 based programmer (ex: JTAG HS2).	2020-11-23 10:13:57 +01:00
targets	targets/xilinx: add false path constraint between sys_clk and pll.clkin.	2021-01-07 00:02:46 +01:00
tools	general: add SPDX License identifier to header and specify files are part of LiteX-Boards.	2020-08-23 15:00:17 +02:00
__init__.py