Florent Kermarrec 1ac1c6857f targets/xilinx: add false path constraint between sys_clk and pll.clkin. ... The SoC reset added recently creates a path between sys_clk and pll.clkin clock domains that is reported by the tools but that can be safely ignored.		2021-01-07 00:02:46 +01:00
..
__init__.py
ac701.py	targets/xilinx: add false path constraint between sys_clk and pll.clkin.	2021-01-07 00:02:46 +01:00
acorn_cle_215.py	targets/xilinx: add false path constraint between sys_clk and pll.clkin.	2021-01-07 00:02:46 +01:00
aller.py	targets/xilinx: add false path constraint between sys_clk and pll.clkin.	2021-01-07 00:02:46 +01:00
alveo_u250.py	targets/xilinx: add false path constraint between sys_clk and pll.clkin.	2021-01-07 00:02:46 +01:00
arty.py	targets/xilinx: add false path constraint between sys_clk and pll.clkin.	2021-01-07 00:02:46 +01:00
arty_s7.py	targets/xilinx: add false path constraint between sys_clk and pll.clkin.	2021-01-07 00:02:46 +01:00
c10lprefkit.py
camlink_4k.py
colorlight_5a_75x.py
crosslink_nx_evn.py
crosslink_nx_vip.py
de0nano.py
de1soc.py
de2_115.py
de10lite.py
de10nano.py
ecp5_evn.py
ecpix5.py
fk33.py	targets/xilinx: add false path constraint between sys_clk and pll.clkin.	2021-01-07 00:02:46 +01:00
fomu.py
genesys2.py	targets/xilinx: add false path constraint between sys_clk and pll.clkin.	2021-01-07 00:02:46 +01:00
hadbadge.py
icebreaker.py
kc705.py	targets/xilinx: add false path constraint between sys_clk and pll.clkin.	2021-01-07 00:02:46 +01:00
kcu105.py	targets/xilinx: add false path constraint between sys_clk and pll.clkin.	2021-01-07 00:02:46 +01:00
kx2.py	targets/xilinx: add false path constraint between sys_clk and pll.clkin.	2021-01-07 00:02:46 +01:00
linsn_rv901t.py
litefury.py	targets/xilinx: add false path constraint between sys_clk and pll.clkin.	2021-01-07 00:02:46 +01:00
logicbone.py
mercury_xu5.py	targets/xilinx: add false path constraint between sys_clk and pll.clkin.	2021-01-07 00:02:46 +01:00
mimas_a7.py	targets/xilinx: add false path constraint between sys_clk and pll.clkin.	2021-01-07 00:02:46 +01:00
minispartan6.py	targets/xilinx: add false path constraint between sys_clk and pll.clkin.	2021-01-07 00:02:46 +01:00
mist.py
nereid.py	targets/xilinx: add false path constraint between sys_clk and pll.clkin.	2021-01-07 00:02:46 +01:00
netv2.py	targets/xilinx: add false path constraint between sys_clk and pll.clkin.	2021-01-07 00:02:46 +01:00
nexys4ddr.py	targets/xilinx: add false path constraint between sys_clk and pll.clkin.	2021-01-07 00:02:46 +01:00
nexys_video.py	targets/xilinx: add false path constraint between sys_clk and pll.clkin.	2021-01-07 00:02:46 +01:00
orangecrab.py
pano_logic_g2.py	targets/xilinx: add false path constraint between sys_clk and pll.clkin.	2021-01-07 00:02:46 +01:00
pipistrello.py
qmtech_ep4ce15.py
qmtech_wukong.py
redpitaya.py	targets/xilinx: add false path constraint between sys_clk and pll.clkin.	2021-01-07 00:02:46 +01:00
sds1104xe.py	targets/xilinx: add false path constraint between sys_clk and pll.clkin.	2021-01-07 00:02:46 +01:00
simple.py
tagus.py	targets/xilinx: add false path constraint between sys_clk and pll.clkin.	2021-01-07 00:02:46 +01:00
tec0117.py
tinyfpga_bx.py
trellisboard.py
ulx3s.py
vc707.py	targets/xilinx: add false path constraint between sys_clk and pll.clkin.	2021-01-07 00:02:46 +01:00
vcu118.py	targets/xilinx: add false path constraint between sys_clk and pll.clkin.	2021-01-07 00:02:46 +01:00
versa_ecp5.py
xcu1525.py	targets/xilinx: add false path constraint between sys_clk and pll.clkin.	2021-01-07 00:02:46 +01:00
zcu104.py	targets/xilinx: add false path constraint between sys_clk and pll.clkin.	2021-01-07 00:02:46 +01:00
zybo_z7.py	targets/xilinx: add false path constraint between sys_clk and pll.clkin.	2021-01-07 00:02:46 +01:00