mirror of
https://github.com/litex-hub/litex-boards.git
synced 2025-01-03 03:43:36 -05:00
1ac1c6857f
The SoC reset added recently creates a path between sys_clk and pll.clkin clock domains that is reported by the tools but that can be safely ignored.
118 lines
4.5 KiB
Python
Executable file
118 lines
4.5 KiB
Python
Executable file
#!/usr/bin/env python3
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#
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# This file is part of LiteX-Boards.
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#
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# Copyright (c) 2020 Gwenhael Goavec-Merou <gwenhael.goavec-merou@trabucayre.com>
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# SPDX-License-Identifier: BSD-2-Clause
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import os
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import argparse
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from migen import *
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from litex_boards.platforms import redpitaya
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from litex.build.xilinx.vivado import vivado_build_args, vivado_build_argdict
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from litex.soc.interconnect import axi
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from litex.soc.interconnect import wishbone
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from litex.soc.cores.clock import *
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from litex.soc.integration.soc_core import *
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from litex.soc.integration.builder import *
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from litex.soc.cores.led import LedChaser
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# CRG ----------------------------------------------------------------------------------------------
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class _CRG(Module):
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def __init__(self, platform, sys_clk_freq, use_ps7_clk=False):
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self.rst = Signal()
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self.clock_domains.cd_sys = ClockDomain()
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# # #
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if use_ps7_clk:
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assert sys_clk_freq == 125e6
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self.comb += ClockSignal("sys").eq(ClockSignal("ps7"))
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self.comb += ResetSignal("sys").eq(ResetSignal("ps7") | self.rst)
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else:
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self.submodules.pll = pll = S7PLL(speedgrade=-1)
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self.comb += pll.reset.eq(self.rst)
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pll.register_clkin(platform.request(platform.default_clk_name), platform.default_clk_freq)
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pll.create_clkout(self.cd_sys, sys_clk_freq)
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platform.add_false_path_constraints(pll.clkin, self.cd_sys.clk)
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# BaseSoC ------------------------------------------------------------------------------------------
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class BaseSoC(SoCCore):
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def __init__(self, board, sys_clk_freq=int(100e6), **kwargs):
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platform = redpitaya.Platform(board)
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if kwargs["uart_name"] == "serial":
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kwargs["uart_name"] = "usb_uart"
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use_ps7_clk = False
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# SoCCore ----------------------------------------------------------------------------------
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SoCCore.__init__(self, platform, sys_clk_freq,
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ident = "LiteX SoC on Zebboard",
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ident_version = True,
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**kwargs)
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# Zynq7000 Integration ---------------------------------------------------------------------
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if kwargs.get("cpu_type", None) == "zynq7000":
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# Get and set the pre-generated .xci FIXME: change location? add it to the repository?
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os.system("wget https://kmf2.trabucayre.com/redpitaya_ps7.txt")
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os.makedirs("xci", exist_ok=True)
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os.system("cp redpitaya_ps7.txt xci/redpitaya_ps7.xci")
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self.cpu.set_ps7_xci("xci/redpitaya_ps7.xci")
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# Connect AXI GP0 to the SoC with base address of 0x43c00000 (default one)
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wb_gp0 = wishbone.Interface()
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self.submodules += axi.AXI2Wishbone(
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axi = self.cpu.add_axi_gp_master(),
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wishbone = wb_gp0,
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base_address = 0x43c00000)
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self.add_wb_master(wb_gp0)
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use_ps7_clk = True
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sys_clk_freq = 125e6
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# CRG --------------------------------------------------------------------------------------
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self.submodules.crg = _CRG(platform, sys_clk_freq, use_ps7_clk)
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# Leds -------------------------------------------------------------------------------------
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self.submodules.leds = LedChaser(
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pads = platform.request_all("user_led"),
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sys_clk_freq = sys_clk_freq)
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self.add_csr("leds")
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# Build --------------------------------------------------------------------------------------------
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def main():
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parser = argparse.ArgumentParser(description="LiteX SoC on Zedboard")
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parser.add_argument("--build", action="store_true", help="Build bitstream")
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parser.add_argument("--load", action="store_true", help="Load bitstream")
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parser.add_argument("--sys-clk-freq", default=100e6, help="System clock frequency (default: 100MHz)")
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parser.add_argument("--board", default="redpitaya14", help="Board type: redpitaya14 (default) or redpitaya16")
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builder_args(parser)
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soc_core_args(parser)
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vivado_build_args(parser)
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args = parser.parse_args()
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soc = BaseSoC(
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board = args.board,
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sys_clk_freq = int(float(args.sys_clk_freq)),
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**soc_core_argdict(args)
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)
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builder = Builder(soc, **builder_argdict(args))
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builder.build(**vivado_build_argdict(args), run=args.build)
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if args.load:
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prog = soc.platform.create_programmer()
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prog.load_bitstream(os.path.join(builder.gateware_dir, soc.build_name + ".bit"), device=1)
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if __name__ == "__main__":
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main()
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