mirror of
https://github.com/litex-hub/litex-boards.git
synced 2025-01-03 03:43:36 -05:00
ba01776432
- main_ram mem_map is now directly used by add_sdram when origin is None. - max_sdram_size/min_l2_data_width are no longer exposed as targets arguments this can still be used enforced directly in the few cases it is useful.
112 lines
4.3 KiB
Python
Executable file
112 lines
4.3 KiB
Python
Executable file
#!/usr/bin/env python3
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#
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# This file is part of LiteX-Boards.
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#
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# Copyright (c) 2020 Antmicro <www.antmicro.com>
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# Copyright (c) 2019 David Shah <dave@ds0.me>
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# SPDX-License-Identifier: BSD-2-Clause
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import os
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import argparse
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from migen import *
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from migen.genlib.resetsync import AsyncResetSynchronizer
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from litex_boards.platforms import zcu104
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from litex.soc.cores.clock import *
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from litex.soc.integration.soc_core import *
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from litex.soc.integration.builder import *
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from litex.soc.cores.led import LedChaser
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from litex.soc.cores.bitbang import I2CMaster
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from litedram.modules import MTA4ATF51264HZ
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from litedram.phy import usddrphy
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# CRG ----------------------------------------------------------------------------------------------
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class _CRG(Module):
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def __init__(self, platform, sys_clk_freq):
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self.rst = Signal()
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self.clock_domains.cd_sys = ClockDomain()
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self.clock_domains.cd_sys4x = ClockDomain(reset_less=True)
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self.clock_domains.cd_pll4x = ClockDomain(reset_less=True)
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self.clock_domains.cd_idelay = ClockDomain()
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# # #
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self.submodules.pll = pll = USMMCM(speedgrade=-2)
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self.comb += pll.reset.eq(self.rst)
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pll.register_clkin(platform.request("clk125"), 125e6)
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pll.create_clkout(self.cd_pll4x, sys_clk_freq*4, buf=None, with_reset=False)
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pll.create_clkout(self.cd_idelay, 500e6)
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platform.add_false_path_constraints(self.cd_sys.clk, pll.clkin) # Ignore sys_clk to pll.clkin path created by SoC's rst.
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self.specials += [
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Instance("BUFGCE_DIV", name="main_bufgce_div",
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p_BUFGCE_DIVIDE=4,
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i_CE=1, i_I=self.cd_pll4x.clk, o_O=self.cd_sys.clk),
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Instance("BUFGCE", name="main_bufgce",
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i_CE=1, i_I=self.cd_pll4x.clk, o_O=self.cd_sys4x.clk),
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]
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self.submodules.idelayctrl = USIDELAYCTRL(cd_ref=self.cd_idelay, cd_sys=self.cd_sys)
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# BaseSoC ------------------------------------------------------------------------------------------
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class BaseSoC(SoCCore):
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def __init__(self, sys_clk_freq=int(125e6), **kwargs):
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platform = zcu104.Platform()
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# SoCCore ----------------------------------------------------------------------------------
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SoCCore.__init__(self, platform, sys_clk_freq,
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ident = "LiteX SoC on ZCU104",
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ident_version = True,
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**kwargs)
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# CRG --------------------------------------------------------------------------------------
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self.submodules.crg = _CRG(platform, sys_clk_freq)
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# DDR4 SDRAM -------------------------------------------------------------------------------
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if not self.integrated_main_ram_size:
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self.submodules.ddrphy = usddrphy.USPDDRPHY(platform.request("ddram"),
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memtype = "DDR4",
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sys_clk_freq = sys_clk_freq,
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iodelay_clk_freq = 500e6)
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self.add_sdram("sdram",
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phy = self.ddrphy,
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module = MTA4ATF51264HZ(sys_clk_freq, "1:4"),
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size = 0x40000000,
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l2_cache_size = kwargs.get("l2_size", 8192)
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)
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# Leds -------------------------------------------------------------------------------------
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self.submodules.leds = LedChaser(
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pads = platform.request_all("user_led"),
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sys_clk_freq = sys_clk_freq)
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# Build --------------------------------------------------------------------------------------------
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def main():
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parser = argparse.ArgumentParser(description="LiteX SoC on ZCU104")
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parser.add_argument("--build", action="store_true", help="Build bitstream")
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parser.add_argument("--load", action="store_true", help="Load bitstream")
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parser.add_argument("--sys-clk-freq", default=125e6, help="System clock frequency (default: 125MHz)")
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builder_args(parser)
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soc_core_args(parser)
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args = parser.parse_args()
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soc = BaseSoC(
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sys_clk_freq = int(float(args.sys_clk_freq)),
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**soc_core_argdict(args)
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)
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builder = Builder(soc, **builder_argdict(args))
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builder.build(run=args.build)
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if args.load:
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prog = soc.platform.create_programmer()
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prog.load_bitstream(os.path.join(builder.gateware_dir, soc.build_name + ".bit"))
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if __name__ == "__main__":
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main()
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