119 lines
4.4 KiB
Python
Executable File
119 lines
4.4 KiB
Python
Executable File
#!/usr/bin/env python3
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# This file is Copyright (c) 2019-2020 Florent Kermarrec <florent@enjoy-digital.fr>
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# License: BSD
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import argparse
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from migen import *
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from litex_boards.platforms import linsn_rv901t
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from litex.soc.integration.soc_sdram import *
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from litex.soc.integration.builder import *
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from litex.soc.cores.clock import S6PLL
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from litedram.modules import M12L64322A
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from litedram.phy import GENSDRPHY
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from liteeth.phy.s6rgmii import LiteEthPHYRGMII
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from liteeth.mac import LiteEthMAC
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# CRG ----------------------------------------------------------------------------------------------
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class _CRG(Module):
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def __init__(self, platform, sys_clk_freq):
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self.clock_domains.cd_sys = ClockDomain()
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self.clock_domains.cd_sys_ps = ClockDomain(reset_less=True)
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# # #
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clk25 = platform.request("clk25")
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platform.add_period_constraint(clk25, 1e9/25e6)
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self.submodules.pll = pll = S6PLL(speedgrade=-2)
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pll.register_clkin(clk25, 25e6)
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pll.create_clkout(self.cd_sys, sys_clk_freq)
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pll.create_clkout(self.cd_sys_ps, sys_clk_freq, phase=270)
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self.specials += Instance("ODDR2",
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p_DDR_ALIGNMENT="NONE",
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p_INIT=0, p_SRTYPE="SYNC",
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i_D0=0, i_D1=1, i_S=0, i_R=0, i_CE=1,
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i_C0=self.cd_sys.clk, i_C1=~self.cd_sys.clk,
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o_Q=platform.request("sdram_clock"))
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# BaseSoC ------------------------------------------------------------------------------------------
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class BaseSoC(SoCSDRAM):
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def __init__(self, **kwargs):
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platform = linsn_rv901t.Platform()
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sys_clk_freq = int(75e6)
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# SoCSDRAM ---------------------------------------------------------------------------------
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SoCSDRAM.__init__(self, platform, clk_freq=sys_clk_freq, **kwargs)
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# CRG --------------------------------------------------------------------------------------
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self.submodules.crg = _CRG(platform, sys_clk_freq)
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# SDR SDRAM --------------------------------------------------------------------------------
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self.submodules.sdrphy = GENSDRPHY(platform.request("sdram"))
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sdram_module = M12L64322A(sys_clk_freq, "1:1")
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self.register_sdram(self.sdrphy, sdram_module.geom_settings, sdram_module.timing_settings)
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# EthernetSoC --------------------------------------------------------------------------------------
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class EthernetSoC(BaseSoC):
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mem_map = {
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"ethmac": 0xb0000000,
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}
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mem_map.update(BaseSoC.mem_map)
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def __init__(self, eth_phy=0, **kwargs):
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BaseSoC.__init__(self, **kwargs)
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# Ethernet ---------------------------------------------------------------------------------
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# phy
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self.submodules.ethphy = LiteEthPHYRGMII(
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clock_pads = self.platform.request("eth_clocks", eth_phy),
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pads = self.platform.request("eth", eth_phy))
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self.add_csr("ethphy")
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# mac
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self.submodules.ethmac = LiteEthMAC(
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phy = self.ethphy,
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dw = 32,
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interface = "wishbone",
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endianness = self.cpu.endianness)
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self.add_memory_region("ethmac", self.mem_map["ethmac"], 0x2000, type="io")
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self.add_wb_slave(self.mem_map["ethmac"], self.ethmac.bus, 0x2000)
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self.add_csr("ethmac")
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self.add_interrupt("ethmac")
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# timing constraints
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self.platform.add_period_constraint(self.ethphy.crg.cd_eth_rx.clk, 1e9/125e6)
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self.platform.add_period_constraint(self.ethphy.crg.cd_eth_tx.clk, 1e9/125e6)
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self.platform.add_false_path_constraints(
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self.crg.cd_sys.clk,
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self.ethphy.crg.cd_eth_rx.clk,
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self.ethphy.crg.cd_eth_tx.clk)
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# Build --------------------------------------------------------------------------------------------
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def main():
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parser = argparse.ArgumentParser(description="LiteX SoC on Linsn RV901T")
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builder_args(parser)
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soc_sdram_args(parser)
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parser.add_argument("--with-ethernet", action="store_true", help="enable Ethernet support")
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parser.add_argument("--eth-phy", default=0, type=int, help="Ethernet PHY 0 or 1 (default=0)")
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args = parser.parse_args()
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if args.with_ethernet:
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soc = EthernetSoC(eth_phy=args.eth_phy, **soc_sdram_argdict(args))
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else:
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soc = BaseSoC(**soc_sdram_argdict(args))
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builder = Builder(soc, **builder_argdict(args))
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builder.build()
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if __name__ == "__main__":
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main()
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