litex-boards/litex_boards/targets
Florent Kermarrec 6ab13a0661 de10nano/MiSTer: rename SPI SD CARD pins to spisdcard and remove SPI SD Card integration from target. 2020-03-19 11:09:48 +01:00
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__init__.py Avoid Official/Partner/Community differentiation: use same directory for all platforms/targets. 2020-02-03 09:36:30 +01:00
ac701.py targets: avoid direct use of mem_decoder. 2020-02-11 21:59:42 +01:00
aller.py Avoid Official/Partner/Community differentiation: use same directory for all platforms/targets. 2020-02-03 09:36:30 +01:00
arty.py platforms/targets: keep in sync with LiteX 2020-02-27 11:06:53 +01:00
c10lprefkit.py targets: avoid direct use of mem_decoder. 2020-02-11 21:59:42 +01:00
camlink_4k.py targets/ecp5: make sure all BaseSoC/EthernetSoc default to trellis. 2020-03-05 10:57:59 +01:00
colorlight_5a_75b.py targets: default to trellis toolchain on all ECP5 targets (now able to build all supported targets). 2020-02-28 09:46:54 +01:00
de0nano.py Avoid Official/Partner/Community differentiation: use same directory for all platforms/targets. 2020-02-03 09:36:30 +01:00
de1soc.py Avoid Official/Partner/Community differentiation: use same directory for all platforms/targets. 2020-02-03 09:36:30 +01:00
de2_115.py Avoid Official/Partner/Community differentiation: use same directory for all platforms/targets. 2020-02-03 09:36:30 +01:00
de10lite.py targets: avoid direct use of mem_decoder. 2020-02-11 21:59:42 +01:00
de10nano.py de10nano/MiSTer: rename SPI SD CARD pins to spisdcard and remove SPI SD Card integration from target. 2020-03-19 11:09:48 +01:00
ecp5_evn.py targets/ecp5: make sure all BaseSoC/EthernetSoc default to trellis. 2020-03-05 10:57:59 +01:00
fomu.py Changed wrong imports for fomu board. 2020-02-12 12:40:07 +01:00
genesys2.py Avoid Official/Partner/Community differentiation: use same directory for all platforms/targets. 2020-02-03 09:36:30 +01:00
hadbadge.py targets/ecp5: make sure all BaseSoC/EthernetSoc default to trellis. 2020-03-05 10:57:59 +01:00
icebreaker.py targets/icebreaker: use simplified version closer to the others targets. 2020-03-13 09:43:43 +01:00
kc705.py targets/kc705: use DDRPHY_CMD_DELAY to center write leveling. 2020-02-27 12:58:52 +01:00
kcu105.py targets/Ultrascale(+): simplify CRG using USIDELAYCTRL. 2020-03-10 16:55:22 +01:00
kx2.py Avoid Official/Partner/Community differentiation: use same directory for all platforms/targets. 2020-02-03 09:36:30 +01:00
linsn_rv901t.py targets/EthernetSoC: be sure memory region is added before adding Wishbone Slave (required by new SoC) 2020-02-11 17:45:35 +01:00
mercury_xu5.py targets/Ultrascale+: use 500MHz IDELAYCTRL reference clock. 2020-03-10 16:58:30 +01:00
mimas_a7.py targets/EthernetSoC: be sure memory region is added before adding Wishbone Slave (required by new SoC) 2020-02-11 17:45:35 +01:00
minispartan6.py Avoid Official/Partner/Community differentiation: use same directory for all platforms/targets. 2020-02-03 09:36:30 +01:00
nereid.py Avoid Official/Partner/Community differentiation: use same directory for all platforms/targets. 2020-02-03 09:36:30 +01:00
netv2.py targets/EthernetSoC: be sure memory region is added before adding Wishbone Slave (required by new SoC) 2020-02-11 17:45:35 +01:00
nexys4ddr.py targets/EthernetSoC: be sure memory region is added before adding Wishbone Slave (required by new SoC) 2020-02-11 17:45:35 +01:00
nexys_video.py Avoid Official/Partner/Community differentiation: use same directory for all platforms/targets. 2020-02-03 09:36:30 +01:00
orangecrab.py targets/ecp5: make sure all BaseSoC/EthernetSoc default to trellis. 2020-03-05 10:57:59 +01:00
pipistrello.py Avoid Official/Partner/Community differentiation: use same directory for all platforms/targets. 2020-02-03 09:36:30 +01:00
simple.py targets/EthernetSoC: be sure memory region is added before adding Wishbone Slave (required by new SoC) 2020-02-11 17:45:35 +01:00
tagus.py Avoid Official/Partner/Community differentiation: use same directory for all platforms/targets. 2020-02-03 09:36:30 +01:00
trellisboard.py targets/ecp5: make sure all BaseSoC/EthernetSoc default to trellis. 2020-03-05 10:57:59 +01:00
ulx3s.py targets: default to trellis toolchain on all ECP5 targets (now able to build all supported targets). 2020-02-28 09:46:54 +01:00
vc707.py vc707: fix copyrights (Michael Betz is the initial author) 2020-02-28 08:39:52 +01:00
vcu118.py targets/Ultrascale+: use 500MHz IDELAYCTRL reference clock. 2020-03-10 16:58:30 +01:00
versa_ecp5.py targets/ecp5: make sure all BaseSoC/EthernetSoc default to trellis. 2020-03-05 10:57:59 +01:00
zcu104.py targets/Ultrascale(+): simplify CRG using USIDELAYCTRL. 2020-03-10 16:55:22 +01:00