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targets: avoid direct use of mem_decoder.

This commit is contained in:
Florent Kermarrec 2020-02-11 21:59:42 +01:00
parent 4edf196911
commit c94360c2e0
3 changed files with 2 additions and 4 deletions
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1
litex_boards/targets/ac701.py
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@ -11,7 +11,6 @@ from migen import *
from litex_boards.platforms import ac701
from litex.soc.cores.clock import *
from litex.soc.integration.soc_core import mem_decoder
from litex.soc.integration.soc_sdram import *
from litex.soc.integration.builder import *

2
litex_boards/targets/c10lprefkit.py
View File

@ -101,7 +101,7 @@ class BaseSoC(SoCSDRAM):
# HyperRam ---------------------------------------------------------------------------------
self.submodules.hyperram = HyperRAM(platform.request("hyperram"))
self.add_wb_slave(mem_decoder(self.mem_map["hyperram"]), self.hyperram.bus)
self.add_wb_slave(self.mem_map["hyperram"], self.hyperram.bus)
self.add_memory_region("hyperram", self.mem_map["hyperram"], 8*1024*1024)
# SDR SDRAM --------------------------------------------------------------------------------

3
litex_boards/targets/de10lite.py
View File

@ -12,7 +12,6 @@ from litex_boards.platforms import de10lite
from litex.soc.integration.soc_sdram import *
from litex.soc.integration.builder import *
from litex.soc.integration.soc_core import mem_decoder
from litedram.modules import IS42S16320
from litedram.phy import GENSDRPHY
@ -111,7 +110,7 @@ class VGASoC(BaseSoC):
# create VGA terminal
self.submodules.terminal = terminal = Terminal()
self.add_wb_slave(mem_decoder(self.mem_map["terminal"]), self.terminal.bus)
self.add_wb_slave(self.mem_map["terminal"], self.terminal.bus)
self.add_memory_region("terminal", self.mem_map["terminal"], 0x10000)
# connect VGA pins