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targets/EthernetSoC: be sure memory region is added before adding Wishbone Slave (required by new SoC)

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This commit is contained in:
Florent Kermarrec 2020-02-11 17:45:35 +01:00
parent 83c48946ad
commit 4edf196911
12 changed files with 12 additions and 12 deletions
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2
litex_boards/targets/ac701.py
View file

@ -131,8 +131,8 @@ class EthernetSoC(BaseSoC):
dw = 32,
interface = "wishbone",
endianness = self.cpu.endianness)
self.add_wb_slave(mem_decoder(self.mem_map["ethmac"]), self.ethmac.bus)
self.add_memory_region("ethmac", self.mem_map["ethmac"], 0x2000, type="io")
self.add_wb_slave(self.mem_map["ethmac"], self.ethmac.bus, 0x2000)
self.add_csr("ethmac")
self.add_interrupt("ethmac")

2
litex_boards/targets/arty.py
View file

@ -94,8 +94,8 @@ class EthernetSoC(BaseSoC):
dw = 32,
interface = "wishbone",
endianness = self.cpu.endianness)
self.add_wb_slave(self.mem_map["ethmac"], self.ethmac.bus, 0x2000)
self.add_memory_region("ethmac", self.mem_map["ethmac"], 0x2000, type="io")
self.add_wb_slave(self.mem_map["ethmac"], self.ethmac.bus, 0x2000)
self.add_csr("ethmac")
self.add_interrupt("ethmac")
# timing constraints

2
litex_boards/targets/c10lprefkit.py
View file

@ -135,8 +135,8 @@ class EthernetSoC(BaseSoC):
dw = 32,
interface = "wishbone",
endianness = self.cpu.endianness)
self.add_wb_slave(self.mem_map["ethmac"], self.ethmac.bus, 0x2000)
self.add_memory_region("ethmac", self.mem_map["ethmac"], 0x2000, type="io")
self.add_wb_slave(self.mem_map["ethmac"], self.ethmac.bus, 0x2000)
self.add_csr("ethmac")
self.add_interrupt("ethmac")
# timing constraints

2
litex_boards/targets/kc705.py
View file

@ -88,8 +88,8 @@ class EthernetSoC(BaseSoC):
dw = 32,
interface = "wishbone",
endianness = self.cpu.endianness)
self.add_wb_slave(self.mem_map["ethmac"], self.ethmac.bus, 0x2000)
self.add_memory_region("ethmac", self.mem_map["ethmac"], 0x2000, type="io")
self.add_wb_slave(self.mem_map["ethmac"], self.ethmac.bus, 0x2000)
self.add_csr("ethmac")
self.add_interrupt("ethmac")
# timing constraints

2
litex_boards/targets/kcu105.py
View file

@ -123,8 +123,8 @@ class EthernetSoC(BaseSoC):
dw = 32,
interface = "wishbone",
endianness = self.cpu.endianness)
self.add_wb_slave(self.mem_map["ethmac"], self.ethmac.bus, 0x2000)
self.add_memory_region("ethmac", self.mem_map["ethmac"], 0x2000, type="io")
self.add_wb_slave(self.mem_map["ethmac"], self.ethmac.bus, 0x2000)
self.add_csr("ethmac")
self.add_interrupt("ethmac")
# timing constraints

2
litex_boards/targets/linsn_rv901t.py
View file

@ -84,8 +84,8 @@ class EthernetSoC(BaseSoC):
dw = 32,
interface = "wishbone",
endianness = self.cpu.endianness)
self.add_wb_slave(self.mem_map["ethmac"], self.ethmac.bus, 0x2000)
self.add_memory_region("ethmac", self.mem_map["ethmac"], 0x2000, type="io")
self.add_wb_slave(self.mem_map["ethmac"], self.ethmac.bus, 0x2000)
self.add_csr("ethmac")
self.add_interrupt("ethmac")
# timing constraints

2
litex_boards/targets/mimas_a7.py
View file

@ -86,8 +86,8 @@ class EthernetSoC(BaseSoC):
# mac
self.submodules.ethmac = LiteEthMAC(phy=self.ethphy, dw=32,
interface="wishbone", endianness=self.cpu.endianness)
self.add_wb_slave(self.mem_map["ethmac"], self.ethmac.bus, 0x2000)
self.add_memory_region("ethmac", self.mem_map["ethmac"], 0x2000, type="io")
self.add_wb_slave(self.mem_map["ethmac"], self.ethmac.bus, 0x2000)
self.add_csr("ethmac")
self.add_interrupt("ethmac")
# timing constraints

2
litex_boards/targets/netv2.py
View file

@ -90,8 +90,8 @@ class EthernetSoC(BaseSoC):
dw = 32,
interface = "wishbone",
endianness = self.cpu.endianness)
self.add_wb_slave(self.mem_map["ethmac"], self.ethmac.bus, 0x2000)
self.add_memory_region("ethmac", self.mem_map["ethmac"], 0x2000, type="io")
self.add_wb_slave(self.mem_map["ethmac"], self.ethmac.bus, 0x2000)
self.add_csr("ethmac")
self.add_interrupt("ethmac")
# timing constraints

2
litex_boards/targets/nexys4ddr.py
View file

@ -89,8 +89,8 @@ class EthernetSoC(BaseSoC):
dw = 32,
interface = "wishbone",
endianness = self.cpu.endianness)
self.add_wb_slave(self.mem_map["ethmac"], self.ethmac.bus, 0x2000)
self.add_memory_region("ethmac", self.mem_map["ethmac"], 0x2000, type="io")
self.add_wb_slave(self.mem_map["ethmac"], self.ethmac.bus, 0x2000)
self.add_csr("ethmac")
self.add_interrupt("ethmac")
# timing constraints

2
litex_boards/targets/simple.py
View file

@ -48,8 +48,8 @@ class EthernetSoC(BaseSoC):
# mac
self.submodules.ethmac = LiteEthMAC(phy=self.ethphy, dw=32,
interface="wishbone", endianness=self.cpu.endianness, with_preamble_crc=False)
self.add_wb_slave(self.mem_map["ethmac"], self.ethmac.bus, 0x2000)
self.add_memory_region("ethmac", self.mem_map["ethmac"], 0x2000, type="io")
self.add_wb_slave(self.mem_map["ethmac"], self.ethmac.bus, 0x2000)
self.add_csr("ethmac")
self.add_interrupt("ethmac")

2
litex_boards/targets/trellisboard.py
View file

@ -120,8 +120,8 @@ class EthernetSoC(BaseSoC):
# mac
self.submodules.ethmac = LiteEthMAC(phy=self.ethphy, dw=32,
interface="wishbone", endianness=self.cpu.endianness)
self.add_wb_slave(self.mem_map["ethmac"], self.ethmac.bus, 0x2000)
self.add_memory_region("ethmac", self.mem_map["ethmac"], 0x2000, type="io")
self.add_wb_slave(self.mem_map["ethmac"], self.ethmac.bus, 0x2000)
self.add_csr("ethmac")
self.add_interrupt("ethmac")
# timing constraints

2
litex_boards/targets/versa_ecp5.py
View file

@ -114,8 +114,8 @@ class EthernetSoC(BaseSoC):
# mac
self.submodules.ethmac = LiteEthMAC(phy=self.ethphy, dw=32,
interface="wishbone", endianness=self.cpu.endianness)
self.add_wb_slave(self.mem_map["ethmac"], self.ethmac.bus, 0x2000)
self.add_memory_region("ethmac", self.mem_map["ethmac"], 0x2000, type="io")
self.add_wb_slave(self.mem_map["ethmac"], self.ethmac.bus, 0x2000)
self.add_csr("ethmac")
self.add_interrupt("ethmac")
# timing constraints