litex-boards/litex_boards
Ilia Sergachev 43a1e13b53 zedboard: compress bitstream, derive default clk f 2021-12-22 03:13:30 +01:00
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platforms zedboard: compress bitstream, derive default clk f 2021-12-22 03:13:30 +01:00
prog prog/openocd_butterstick: Set _CHIPNAME to ecp5 (for jtag_uart/jtag_bone). 2021-10-27 17:27:07 +02:00
targets Efinix: ti60: add HyperRAM support 2021-12-17 10:23:10 +01:00
tools general: add SPDX License identifier to header and specify files are part of LiteX-Boards. 2020-08-23 15:00:17 +02:00
__init__.py efinix_trion_t120_bga576_dev_kit: Remove debug, integrate LPDDR3 as done on other targets. 2021-11-12 18:04:30 +01:00