157 lines
6.5 KiB
Python
Executable File
157 lines
6.5 KiB
Python
Executable File
#!/usr/bin/env python3
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# This file is Copyright (c) Greg Davill <greg.davill@gmail.com>
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# License: BSD
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import argparse
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from migen import *
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from migen.genlib.resetsync import AsyncResetSynchronizer
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from litex_boards.platforms import orangecrab
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from litex.build.lattice.trellis import trellis_args, trellis_argdict
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from litex.soc.cores.clock import *
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from litex.soc.integration.soc_core import *
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from litex.soc.integration.soc_sdram import *
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from litex.soc.integration.builder import *
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from litedram.modules import MT41K64M16, MT41K128M16, MT41K256M16
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from litedram.phy import ECP5DDRPHY
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# _CRG ---------------------------------------------------------------------------------------------
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class _CRG(Module):
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def __init__(self, platform, sys_clk_freq, with_usb_pll=False):
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self.clock_domains.cd_init = ClockDomain()
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self.clock_domains.cd_por = ClockDomain(reset_less=True)
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self.clock_domains.cd_sys = ClockDomain()
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self.clock_domains.cd_sys2x = ClockDomain()
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self.clock_domains.cd_sys2x_i = ClockDomain(reset_less=True)
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self.clock_domains.cd_sys2x_eb = ClockDomain(reset_less=True)
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# # #
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self.stop = Signal()
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# Clk / Rst
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clk48 = platform.request("clk48")
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platform.add_period_constraint(clk48, 1e9/48e6)
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# Power on reset
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por_count = Signal(16, reset=2**16-1)
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por_done = Signal()
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self.comb += self.cd_por.clk.eq(ClockSignal())
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self.comb += por_done.eq(por_count == 0)
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self.sync.por += If(~por_done, por_count.eq(por_count - 1))
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# PLL
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sys2x_clk_ecsout = Signal()
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self.submodules.pll = pll = ECP5PLL()
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pll.register_clkin(clk48, 48e6)
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pll.create_clkout(self.cd_sys2x_i, 2*sys_clk_freq)
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pll.create_clkout(self.cd_init, 24e6)
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self.specials += [
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Instance("ECLKBRIDGECS",
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i_CLK0 = self.cd_sys2x_i.clk,
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i_SEL = 0,
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o_ECSOUT = sys2x_clk_ecsout),
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Instance("ECLKSYNCB",
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i_ECLKI = sys2x_clk_ecsout,
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i_STOP = self.stop,
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o_ECLKO = self.cd_sys2x.clk),
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Instance("CLKDIVF",
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p_DIV = "2.0",
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i_ALIGNWD = 0,
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i_CLKI = self.cd_sys2x.clk,
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i_RST = self.cd_sys2x.rst,
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o_CDIVX = self.cd_sys.clk),
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AsyncResetSynchronizer(self.cd_init, ~por_done | ~pll.locked),
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AsyncResetSynchronizer(self.cd_sys, ~por_done | ~pll.locked)
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]
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# USB PLL
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if with_usb_pll:
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self.clock_domains.cd_usb_12 = ClockDomain()
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self.clock_domains.cd_usb_48 = ClockDomain()
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usb_pll = ECP5PLL()
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self.submodules += usb_pll
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usb_pll.register_clkin(clk48, 48e6)
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usb_pll.create_clkout(self.cd_usb_48, 48e6)
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usb_pll.create_clkout(self.cd_usb_12, 12e6)
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# BaseSoC ------------------------------------------------------------------------------------------
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class BaseSoC(SoCCore):
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def __init__(self, sys_clk_freq=int(48e6), toolchain="trellis", **kwargs):
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# Board Revision ---------------------------------------------------------------------------
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revision = kwargs.get("revision", "0.2")
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device = kwargs.get("device", "25F")
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platform = orangecrab.Platform(revision=revision, device=device ,toolchain=toolchain)
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# Serial -----------------------------------------------------------------------------------
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platform.add_extension(orangecrab.feather_serial)
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# SoCCore ----------------------------------------------------------------------------------
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SoCCore.__init__(self, platform, clk_freq=sys_clk_freq, **kwargs)
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# CRG --------------------------------------------------------------------------------------
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with_usb_pll = kwargs.get("uart_name", None) == "usb_cdc"
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self.submodules.crg = _CRG(platform, sys_clk_freq, with_usb_pll)
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# DDR3 SDRAM -------------------------------------------------------------------------------
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if not self.integrated_main_ram_size:
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available_sdram_modules = {
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'MT41K64M16': MT41K64M16,
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'MT41K128M16': MT41K128M16,
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'MT41K256M16': MT41K256M16,
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# 'MT41K512M16': MT41K512M16
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}
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sdram_module = available_sdram_modules.get(
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kwargs.get("sdram_device", "MT41K64M16"))
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self.submodules.ddrphy = ECP5DDRPHY(
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platform.request("ddram"),
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sys_clk_freq=sys_clk_freq)
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self.add_csr("ddrphy")
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self.add_constant("ECP5DDRPHY")
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self.comb += self.crg.stop.eq(self.ddrphy.init.stop)
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self.add_sdram("sdram",
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phy = self.ddrphy,
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module = sdram_module(sys_clk_freq, "1:2"),
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origin = self.mem_map["main_ram"],
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size = kwargs.get("max_sdram_size", 0x40000000),
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l2_cache_size = kwargs.get("l2_size", 8192),
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l2_cache_min_data_width = kwargs.get("min_l2_data_width", 128),
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l2_cache_reverse = True
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)
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# Build --------------------------------------------------------------------------------------------
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def main():
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parser = argparse.ArgumentParser(description="LiteX SoC on OrangeCrab")
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parser.add_argument("--gateware-toolchain", dest="toolchain", default="trellis",
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help="gateware toolchain to use, trellis (default) or diamond")
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builder_args(parser)
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soc_sdram_args(parser)
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trellis_args(parser)
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parser.add_argument("--sys-clk-freq", default=48e6,
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help="system clock frequency (default=48MHz)")
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parser.add_argument("--revision", default="0.2",
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help="Board Revision {0.1, 0.2} (default=0.2)")
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parser.add_argument("--device", default="25F",
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help="ECP5 device (default=25F)")
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parser.add_argument("--sdram-device", default="MT41K64M16",
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help="ECP5 device (default=MT41K64M16)")
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args = parser.parse_args()
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soc = BaseSoC(toolchain=args.toolchain, sys_clk_freq=int(float(args.sys_clk_freq)), **soc_sdram_argdict(args))
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builder = Builder(soc, **builder_argdict(args))
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builder_kargs = trellis_argdict(args) if args.toolchain == "trellis" else {}
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builder.build(**builder_kargs)
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if __name__ == "__main__":
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main()
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