mirror of
https://github.com/litex-hub/litex-boards.git
synced 2025-01-03 03:43:36 -05:00
55ea71bd01
Validated with:
./gsd_butterstick.py --uart-name=crossover --with-etherbone --csr-csv=csr.csv --build --load
litex_server --udp
litex_term bridge
__ _ __ _ __
/ / (_) /____ | |/_/
/ /__/ / __/ -_)> <
/____/_/\__/\__/_/|_|
Build your hardware, easily!
(c) Copyright 2012-2021 Enjoy-Digital
(c) Copyright 2007-2015 M-Labs
BIOS built on Sep 1 2021 19:09:52
BIOS CRC passed (3d349845)
Migen git sha1: 27dbf03
LiteX git sha1: 315fbe18
--=============== SoC ==================--
CPU: VexRiscv @ 75MHz
BUS: WISHBONE 32-bit @ 4GiB
CSR: 32-bit data
ROM: 128KiB
SRAM: 8KiB
L2: 8KiB
SDRAM: 524288KiB 16-bit @ 300MT/s (CL-6 CWL-5)
--========== Initialization ============--
Initializing SDRAM @0x40000000...
Switching SDRAM to software control.
Read leveling:
m0, b00: |01110000| delays: 02+-01
m0, b01: |00000000| delays: -
m0, b02: |00000000| delays: -
m0, b03: |00000000| delays: -
best: m0, b00 delays: 02+-01
m1, b00: |01110000| delays: 02+-01
m1, b01: |00000000| delays: -
m1, b02: |00000000| delays: -
m1, b03: |00000000| delays: -
best: m1, b00 delays: 02+-01
Switching SDRAM to hardware control.
Memtest at 0x40000000 (2.0MiB)...
Write: 0x40000000-0x40200000 2.0MiB
Read: 0x40000000-0x40200000 2.0MiB
Memtest OK
Memspeed at 0x40000000 (Sequential, 2.0MiB)...
Write speed: 13.6MiB/s
Read speed: 15.6MiB/s
--============== Boot ==================--
Booting from serial...
Press Q or ESC to abort boot completely.
sL5DdSMmkekro
Timeout
No boot medium found
--============= Console ================--
litex>
102 lines
4 KiB
Python
102 lines
4 KiB
Python
#
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# This file is part of LiteX-Boards.
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#
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# Copyright (c) 2021 Greg Davill <greg.davill@gmail.com>
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# Copyright (c) 2021 Florent Kermarrec <florent@enjoy-digital.fr>
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# SPDX-License-Identifier: BSD-2-Clause
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from litex.build.generic_platform import *
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from litex.build.lattice import LatticePlatform
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from litex.build.lattice.programmer import OpenOCDJTAGProgrammer
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# IOs ----------------------------------------------------------------------------------------------
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_io_r1_0 = [
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# Clk
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("clk30", 0, Pins("B12"), IOStandard("LVCMOS33")),
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# Leds
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("user_led", 0, Pins("C13"), IOStandard("LVCMOS33")),
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("user_led", 1, Pins("D12"), IOStandard("LVCMOS33")),
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("user_led", 2, Pins(" U2"), IOStandard("LVCMOS33")),
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("user_led", 3, Pins(" T3"), IOStandard("LVCMOS33")),
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("user_led", 4, Pins("D13"), IOStandard("LVCMOS33")),
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("user_led", 5, Pins("E13"), IOStandard("LVCMOS33")),
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("user_led", 6, Pins("C16"), IOStandard("LVCMOS33")),
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("user_led_color", 0, Pins("T1 R1 U1"), IOStandard("LVCMOS33")),
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# Buttons
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("user_btn", 0, Pins("U16"), IOStandard("SSTL135_I")),
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("user_btn", 1, Pins("T17"), IOStandard("SSTL135_I")),
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# DDR3 SDRAM
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("ddram", 0,
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Subsignal("a", Pins(
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"G16 E19 E20 F16 F19 E16 F17 L20 "
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"M20 E18 G18 D18 H18 C18 D17 G20 "),
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IOStandard("SSTL135_I")),
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Subsignal("ba", Pins("H16 F20 H20"), IOStandard("SSTL135_I")),
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Subsignal("ras_n", Pins("K18"), IOStandard("SSTL135_I")),
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Subsignal("cas_n", Pins("J17"), IOStandard("SSTL135_I")),
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Subsignal("we_n", Pins("G19"), IOStandard("SSTL135_I")),
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Subsignal("cs_n", Pins("J20 J16"), IOStandard("SSTL135_I")),
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Subsignal("dm", Pins("U20 L18"), IOStandard("SSTL135_I")),
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Subsignal("dq", Pins(
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"U19 T18 U18 R20 P18 P19 P20 N20",
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"L19 L17 L16 R16 N18 R17 N17 P17"),
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IOStandard("SSTL135_I"),
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Misc("TERMINATION=75")),
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Subsignal("dqs_p", Pins("T19 N16"), IOStandard("SSTL135D_I"),
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Misc("TERMINATION=OFF"),
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Misc("DIFFRESISTOR=100")),
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Subsignal("clk_p", Pins("C20 J19"), IOStandard("SSTL135D_I")),
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Subsignal("cke", Pins("F18 J18"), IOStandard("SSTL135_I")),
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Subsignal("odt", Pins("K20 H17"), IOStandard("SSTL135_I")),
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Subsignal("reset_n", Pins("E17"), IOStandard("SSTL135_I")),
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Misc("SLEWRATE=FAST")
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),
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# RGMII Ethernet
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("eth_clocks", 0,
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Subsignal("tx", Pins("E15")),
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Subsignal("rx", Pins("D11")),
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IOStandard("LVCMOS33"),
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Misc("SLEWRATE=FAST"),
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),
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("eth", 0,
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Subsignal("rst_n", Pins("B20")),
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Subsignal("mdio", Pins("D16")),
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Subsignal("mdc", Pins("A19")),
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Subsignal("rx_data", Pins("A16 C17 B17 A17")),
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Subsignal("tx_ctl", Pins("D15")),
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Subsignal("rx_ctl", Pins("B18")),
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Subsignal("tx_data", Pins("C15 B16 A18 B19")),
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IOStandard("LVCMOS33"),
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Misc("SLEWRATE=FAST")
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),
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]
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# Connectors ---------------------------------------------------------------------------------------
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_connectors_r1_0 = []
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# Platform -----------------------------------------------------------------------------------------
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class Platform(LatticePlatform):
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default_clk_name = "clk30"
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default_clk_period = 1e9/30e6
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def __init__(self, revision="1.0", device="85F", toolchain="trellis", **kwargs):
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assert revision in ["1.0"]
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self.revision = revision
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io = {"1.0": _io_r1_0}[revision]
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connectors = {"1.0": _connectors_r1_0}[revision]
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LatticePlatform.__init__(self, f"LFE5UM5G-{device}-8BG381C", io, connectors, toolchain=toolchain, **kwargs)
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def create_programmer(self):
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return OpenOCDJTAGProgrammer("openocd_butterstick.cfg")
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def do_finalize(self, fragment):
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LatticePlatform.do_finalize(self, fragment)
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self.add_period_constraint(self.lookup_request("clk30", loose=True), 1e9/30e6)
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