enjoy-digital 5b28c619d5 Merge pull request #178 from yetifrisstlama/vc707_clk ... fix vc707 default_clk_period		2021-02-23 12:17:45 +01:00
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platforms	Merge pull request #178 from yetifrisstlama/vc707_clk	2021-02-23 12:17:45 +01:00
prog	Add FPC-III board support.	2021-01-28 09:51:42 -07:00
targets	targets/sds1104xe/BaseSoC: Enable Etherbone by default also defaults to Crossover UART when kwargs is empty.	2021-02-18 19:30:05 +01:00
tools	general: add SPDX License identifier to header and specify files are part of LiteX-Boards.	2020-08-23 15:00:17 +02:00
__init__.py	init repo with litex official boards	2019-06-10 17:11:36 +02:00