59 lines
2.1 KiB
Python
Executable File
59 lines
2.1 KiB
Python
Executable File
#!/usr/bin/env python3
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#
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# This file is part of LiteX-Boards.
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#
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# Copyright (c) 2022 Joseph FAYE <joseph-wagane.faye@insa-rennes.fr>
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# SPDX-License-Identifier: BSD-2-Clause
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from migen import *
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from litex.gen import *
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from litex_boards.platforms import xilinx_zcu102
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from litex.build.io import CRG
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from litex.soc.integration.soc_core import *
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from litex.soc.integration.builder import *
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from litex.soc.cores.led import LedChaser
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# BaseSoC ------------------------------------------------------------------------------------------
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class BaseSoC(SoCCore):
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def __init__(self, sys_clk_freq=125e6, with_ethernet=False, with_led_chaser=True, **kwargs):
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platform = xilinx_zcu102.Platform()
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# CRG --------------------------------------------------------------------------------------
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self.crg = CRG(platform.request("clk125"))
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# SoCCore ----------------------------------------------------------------------------------
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SoCCore.__init__(self, platform, sys_clk_freq, ident="LiteX SoC on ZCU102", **kwargs)
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# Leds -------------------------------------------------------------------------------------
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if with_led_chaser:
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self.leds = LedChaser(
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pads = platform.request_all("user_led"),
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sys_clk_freq = sys_clk_freq
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)
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# Build --------------------------------------------------------------------------------------------
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def main():
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from litex.build.parser import LiteXArgumentParser
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parser = LiteXArgumentParser(platform=xilinx_zcu102.Platform, description="LiteX SoC on ZCU102.")
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parser.add_target_argument("--sys-clk-freq", default=125e6, type=float, help="System clock generator.")
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args = parser.parse_args()
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soc = BaseSoC(sys_clk_freq=args.sys_clk_freq, **parser.soc_argdict)
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builder = Builder(soc, **parser.builder_argdict)
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if args.build:
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builder.build(**parser.toolchain_argdict)
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if args.load:
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prog = soc.platform.create_programmer()
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prog.load_bitstream(builder.get_bitstream_filename(mode="sram"))
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if __name__ == "__main__":
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main() |