Hardware/litex-boards
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litex-boards/litex_boards
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alainlou 1333f89ed6 rz_easyfpga: adjust SDRAM clk phase 
- also add 1:2 rate
2021-09-22 00:26:28 -04:00
..
platforms rz_easyfpga: adjust SDRAM clk phase 2021-09-22 00:26:28 -04:00
prog
targets rz_easyfpga: adjust SDRAM clk phase 2021-09-22 00:26:28 -04:00
tools
__init__.py Add initial RZ-EasyFPGA support! (#270) 2021-09-21 09:55:22 +02:00