213 lines
9.4 KiB
Markdown
213 lines
9.4 KiB
Markdown
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__ _ __ _ __ ___ __
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/ / (_) /____ | |/_/___/ _ )___ ___ ________/ /__
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/ /__/ / __/ -_)> </___/ _ / _ \/ _ `/ __/ _ (_-<
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/____/_/\__/\__/_/|_| /____/\___/\_,_/_/ \_,_/___/
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LiteX boards files
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Copyright 2012-2022 / LiteX-Hub community
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[](https://github.com/litex-hub/litex-boards/actions) 
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[> Intro
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--------
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<figure>
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<p align="center">
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<img src="https://user-images.githubusercontent.com/1450143/88511626-73792100-cfe5-11ea-8d3e-dbeea6314e15.JPG">
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</p>
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<figcaption>
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<p align="center">
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From the very tiny Fomu to large PCIe accelerator boards....
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</p>
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</figcaption>
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</figure>
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This repository contains the platforms/targets currently supported by LiteX:
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- The platform provides the definition of the board: IOs, constraints, clocks, components + methods to load and flash the bitstream to it.
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- The target provides a LiteX base design for the board that allows you to create a SoC (with or without a CPU) and integrate easily all the base components of your board: Ethernet, DRAM, PCIe, SPIFlash, SDCard, Leds, GPIOs, etc...
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The targets can be used as a base to build more complex or custom SoCs. They are are for example directly reused by the [Linux-on-LiteX-VexRiscv](https://github.com/litex-hub/linux-on-litex-vexriscv) project that is just using a specific configuration (Linux-capable CPU, additional peripherals). Basing your design on provided targets allows to to reduce code duplication between very various projects.
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First make sure to install LiteX correctly by following the [installation guide](https://github.com/enjoy-digital/litex/wiki/Installation) and have a look at the [LiteX's wiki](https://github.com/enjoy-digital/litex/wiki) for [tutorials](https://github.com/enjoy-digital/litex/wiki/Tutorials-Resources), [examples of projects](https://github.com/enjoy-digital/litex/wiki/Projects) and more information to use/build FPGA designs with it.
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Each target provides a default configuration with a CPU, ROM, SRAM, UART, DRAM (if available), Ethernet (if available), etc... that can be simply built and loaded to the FPGA with:
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$ ./target.py --build --load
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You can then open a terminal on the main UART of the board and interact with the LiteX BIOS:
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<p align="center"><img src="https://raw.githubusercontent.com/enjoy-digital/litex/master/doc/bios_screenshot.png"></p>
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But this is just the starting point to create your own hardware! You can then:
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- Change the CPU: add `--cpu-type=lm32, microwatt, serv, rocket, etc... `
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- Change the Bus standard: add `--bus-standard=wishbone, axi-lite`
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- Enable components: add `--with-ethernet --with-etherbone --with-sdcard etc...`
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- [Load application code to the CPU](https://github.com/enjoy-digital/litex/wiki/Load-Application-Code-To-CPU) over UART/Ethernet/SDCard, etc...
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- Create a bridge with your computer to easily [access the main bus of your SoC](https://github.com/enjoy-digital/litex/wiki/Use-Host-Bridge-to-control-debug-a-SoC).
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- Add a Logic Analyzer to your SoC to easily [observe/debug your design](https://github.com/enjoy-digital/litex/wiki/Use-LiteScope-To-Debug-A-SoC).
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- Simulate your SoC and interact with it at decent speed with [LiteX Sim](https://github.com/enjoy-digital/litex/blob/master/litex/tools/litex_sim.py)/Verilator.
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- Integrate external cores/CPU to create your own design.
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- etc...
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Please use `./target.py --help` to see the pre-built various possibilities.
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Hoping you will find this useful and enjoy it, please contribute back if you make improvements that could be useful to others or find issues!
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**A question or want to get in touch? Our IRC channel is [#litex at irc.libera.chat](https://web.libera.chat/#litex)**
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[> Supported boards
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-------------------
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LiteX-Boards currently supports > 120 boards from very various FPGA Vendors (Xilinx, Intel, Lattice, Efinix, Gowin, etc...)!
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Some of these boards are fully open-hardware boards (Fomu, NeTV2, OrangeCrab, Butterstick, etc...) with FPGAs often supported by the open-source toolchains, some of them are repurposed off-the-shelf hardware (Colorlight 5A/I5/I9, SQRL Acorn CLE 215+, FK33, Siglent SDS1104X-E, Decklink Mini 4k, etc...) and we also of course support popular/regular FPGA dev boards :)
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Most of the peripherals present are generally supported: DRAM, UART, Ethernet, SPI-Flash, SDCard, PCIe, SATA, etc... making LiteX-Boards' targets hopefully a good base infrastructure to create your own custom SoCs!
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> **Note:** All boards with >= 32MB of memory and enough logic can be considered as Linux Capable, have a look at [LiteX-on-LiteX-Vexriscv](https://github.com/litex-hub/linux-on-litex-vexriscv) project to try Linux on your FPGA board!
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<figure>
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<p align="center">
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<img src="https://user-images.githubusercontent.com/1450143/156153536-297e2ff8-6ff5-4ec9-a497-b6fa90e26b46.png">
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</p>
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<figcaption>
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<p align="center">
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Some of the suported boards, see yours? Give LiteX-Boards a try!
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</p>
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</figcaption>
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</figure>
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[> Boards list
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---------------
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├── 1bitsquared_icebreaker_bitsy.py
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├── 1bitsquared_icebreaker.py
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├── alchitry_au.py
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├── alchitry_mojo.py
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├── alinx_axu2cga.py
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├── antmicro_datacenter_ddr4_test_board.py
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├── antmicro_lpddr4_test_board.py
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├── avalanche.py
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├── berkeleylab_marblemini.py
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├── berkeleylab_marble.py
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├── camlink_4k.py
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├── colorlight_5a_75b.py
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├── colorlight_5a_75e.py
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├── colorlight_i5.py
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├── decklink_intensity_pro_4k.py
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├── decklink_mini_4k.py
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├── decklink_quad_hdmi_recorder.py
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├── digilent_arty.py
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├── digilent_arty_s7.py
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├── digilent_arty_z7.py
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├── digilent_atlys.py
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├── digilent_basys3.py
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├── digilent_cmod_a7.py
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├── digilent_genesys2.py
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├── digilent_nexys4ddr.py
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├── digilent_nexys4.py
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├── digilent_nexys_video.py
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├── digilent_pynq_z1.py
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├── digilent_zedboard.py
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├── digilent_zybo_z7.py
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├── ebaz4205.py
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├── efinix_titanium_ti60_f225_dev_kit.py
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├── efinix_trion_t120_bga576_dev_kit.py
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├── efinix_trion_t20_bga256_dev_kit.py
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├── efinix_trion_t20_mipi_dev_kit.py
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├── efinix_xyloni_dev_kit.py
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├── ego1.py
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├── enclustra_mercury_kx2.py
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├── enclustra_mercury_xu5.py
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├── fairwaves_xtrx.py
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├── fpc_iii.py
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├── gsd_butterstick.py
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├── gsd_orangecrab.py
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├── hackaday_hadbadge.py
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├── jungle_electronics_fireant.py
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├── kosagi_fomu_evt.py
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├── kosagi_fomu_hacker.py
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├── kosagi_fomu_pvt.py
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├── kosagi_netv2.py
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├── krtkl_snickerdoodle.py
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├── lambdaconcept_ecpix5.py
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├── lattice_crosslink_nx_evn.py
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├── lattice_crosslink_nx_vip.py
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├── lattice_ecp5_evn.py
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├── lattice_ecp5_vip.py
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├── lattice_ice40up5k_evn.py
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├── lattice_machxo3.py
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├── lattice_versa_ecp5.py
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├── linsn_rv901t.py
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├── litex_acorn_baseboard.py
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├── logicbone.py
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├── marblemini.py
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├── marble.py
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├── micronova_mercury2.py
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├── mist.py
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├── mnt_rkx7.py
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├── muselab_icesugar_pro.py
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├── muselab_icesugar.py
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├── myminieye_runber.py
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├── numato_aller.py
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├── numato_mimas_a7.py
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├── numato_nereid.py
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├── numato_tagus.py
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├── pano_logic_g2.py
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├── qmtech_10cl006.py
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├── qmtech_5cefa2.py
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├── qmtech_daughterboard.py
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├── qmtech_ep4cex5.py
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├── qmtech_wukong.py
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├── qmtech_xc7a35t.py
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├── quicklogic_quickfeather.py
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├── qwertyembedded_beaglewire.py
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├── radiona_ulx3s.py
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├── rcs_arctic_tern_bmc_card.py
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├── redpitaya.py
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├── rz_easyfpga.py
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├── saanlima_pipistrello.py
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├── scarabhardware_minispartan6.py
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├── seeedstudio_spartan_edge_accelerator.py
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├── siglent_sds1104xe.py
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├── sipeed_tang_nano_4k.py
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├── sipeed_tang_nano_9k.py
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├── sipeed_tang_nano.py
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├── sipeed_tang_primer.py
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├── sqrl_acorn.py
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├── sqrl_fk33.py
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├── sqrl_xcu1525.py
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├── stlv7325.py
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├── terasic_de0nano.py
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├── terasic_de10lite.py
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├── terasic_de10nano.py
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├── terasic_de1soc.py
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├── terasic_de2_115.py
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├── terasic_deca.py
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├── terasic_sockit.py
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├── tinyfpga_bx.py
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├── trellisboard.py
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├── trenz_c10lprefkit.py
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├── trenz_cyc1000.py
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├── trenz_max1000.py
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├── trenz_te0725.py
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├── trenz_tec0117.py
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├── tul_pynq_z2.py
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├── xilinx_ac701.py
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├── xilinx_alveo_u250.py
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├── xilinx_alveo_u280.py
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├── xilinx_kc705.py
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├── xilinx_kcu105.py
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├── xilinx_kv260.py
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├── xilinx_sp605.py
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├── xilinx_vc707.py
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├── xilinx_vcu118.py
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├── xilinx_zcu104.py
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├── xilinx_zcu106.py
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├── xilinx_zcu216.py
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└── ztex213.py
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