litex-boards/litex_boards
2020-10-13 12:10:29 +02:00
..
platforms platforms/xcu1525: fix ddram constraints, add clk300 constraints for all channels. 2020-10-13 11:50:36 +02:00
prog platforms/genesys2: add openocd specific configuration (channel 1 used for JTAG). 2020-06-23 11:55:50 +02:00
targets targets/xilinx: use generic name for idelay clk (avoid clk200, clk400, etc...) since we somtimes want to change it. 2020-10-13 12:10:29 +02:00
tools general: add SPDX License identifier to header and specify files are part of LiteX-Boards. 2020-08-23 15:00:17 +02:00
__init__.py