litex-boards/litex_boards
2020-02-25 18:32:42 +01:00
..
platforms platforms/vcu118: add missing Internal Vref configuration on DDR4 C1/C2 banks 2020-02-25 18:32:42 +01:00
targets targets/colorlight_5a_75b: add instruction to build/load and use bitstream with wishbone-tool 2020-02-25 12:47:08 +01:00
__init__.py init repo with litex official boards 2019-06-10 17:11:36 +02:00