litex-boards/litex_boards/targets
Florent Kermarrec fff20f7532 targets/fomu: base it on iCEBreaker target + USB-ACM.
This uniformizes Fomu target with others, provide a simple example of LiteX SoC
on Fomu and will ease maintenance.
2020-10-06 11:39:30 +02:00
..
__init__.py
ac701.py targets/ac701: reduce ddram pads to the first 4 modules. 2020-09-05 11:46:07 +02:00
acorn_cle_215.py targets/pcie: update timing_constraints (now provided by the .xci). 2020-09-24 09:50:55 +02:00
aller.py targets/pcie: update timing_constraints (now provided by the .xci). 2020-09-24 09:50:55 +02:00
alveo_u250.py targets/pcie: update timing_constraints (now provided by the .xci). 2020-09-24 09:50:55 +02:00
arty.py
arty_s7.py
c10lprefkit.py
camlink_4k.py
colorlight_5a_75x.py
crosslink_nx_evn.py crosslink_nx_evn: Improve documentation on UART jumpers 2020-09-05 09:58:28 +01:00
de0nano.py
de1soc.py
de2_115.py
de10lite.py
de10nano.py
ecp5_evn.py
ecpix5.py
fk33.py targets/pcie: update timing_constraints (now provided by the .xci). 2020-09-24 09:50:55 +02:00
fomu.py targets/fomu: base it on iCEBreaker target + USB-ACM. 2020-10-06 11:39:30 +02:00
genesys2.py
hadbadge.py
icebreaker.py
kc705.py
kcu105.py targets/kcu105: create specific cd_eth for ethphy. 2020-09-24 10:25:55 +02:00
kx2.py
linsn_rv901t.py
logicbone.py
mercury_xu5.py
mimas_a7.py
minispartan6.py
nereid.py targets/pcie: update timing_constraints (now provided by the .xci). 2020-09-24 09:50:55 +02:00
netv2.py
nexys4ddr.py
nexys_video.py
orangecrab.py
pano_logic_g2.py
pipistrello.py
simple.py
tagus.py targets/pcie: update timing_constraints (now provided by the .xci). 2020-09-24 09:50:55 +02:00
tec0117.py don't verify erase, very slow 2020-10-01 08:41:16 +02:00
trellisboard.py
ulx3s.py
vc707.py
vcu118.py
versa_ecp5.py
xcu1525.py targets/xcu1525: add ddram-channel selection and rewrite DRC workaround comment. 2020-09-24 18:19:49 +02:00
zcu104.py
zybo_z7.py