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8f1350ec40
litex-boards
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litex_boards
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Florent Kermarrec
8f1350ec40
targets/digilent_netfpga_sume.py: Limit mapped SDRAM size as on other targets.
2024-09-20 13:09:48 +02:00
..
platforms
Add support for NetFPGA-Sume (
#604
)
2024-09-18 11:21:51 +02:00
prog
xilinx_zc706: new Xilinx/AMD Zynq7000 based board
2024-03-26 20:49:54 +01:00
targets
targets/digilent_netfpga_sume.py: Limit mapped SDRAM size as on other targets.
2024-09-20 13:09:48 +02:00
__init__.py
litex_boards: Remove short imports since not really longer useful and mess up Python imports.
2022-05-03 17:53:57 +02:00