litex-boards/litex_boards
David Sawatzke 9f5e8d4864 colorlight_5a_75x: Disable full_memory_we for l2 cache by default
Leads to an increase in DP16KD, first noticed in
https://github.com/enjoy-digital/liteeth/issues/70.
With full_mem_we:
```
Info: 	              DP16KD:    41/   56    73%
```
Without:
```
Info: 	              DP16KD:    29/   56    51%
```
2021-08-08 14:37:46 +02:00
..
platforms Merge pull request #245 from racerxdl/feat/MuselabIceSugarPro 2021-07-23 14:34:57 +02:00
prog Add target for LPDDR4 Test Board 2021-03-30 14:50:02 +02:00
targets colorlight_5a_75x: Disable full_memory_we for l2 cache by default 2021-08-08 14:37:46 +02:00
tools
__init__.py __init__.py: Add muselab to vendors. 2021-05-07 09:10:51 +02:00