Gwenhael Goavec-Merou ab732011b3 plaforms/lattice_certuspro_nx_xx: SPI_MASTER_PORT disabled (required to have access to the flash), added default clk period constraints		2024-07-22 14:49:03 +02:00
..
platforms	plaforms/lattice_certuspro_nx_xx: SPI_MASTER_PORT disabled (required to have access to the flash), added default clk period constraints	2024-07-22 14:49:03 +02:00
prog	xilinx_zc706: new Xilinx/AMD Zynq7000 based board	2024-03-26 20:49:54 +01:00
targets	targets: Add initial Enclustra Mercury+ XU8/PE3 target with DRAM and PCIe.	2024-07-22 11:40:19 +02:00
__init__.py	litex_boards: Remove short imports since not really longer useful and mess up Python imports.	2022-05-03 17:53:57 +02:00