78 lines
2.9 KiB
Python
Executable File
78 lines
2.9 KiB
Python
Executable File
#!/usr/bin/env python3
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# This file is Copyright (c) 2019 Arnaud Durand <arnaud.durand@unifr.ch>
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# License: BSD
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import argparse
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from migen import *
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from migen.genlib.resetsync import AsyncResetSynchronizer
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from litex_boards.platforms import ecp5_evn
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from litex.soc.cores.clock import *
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from litex.soc.integration.soc_core import *
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from litex.soc.integration.builder import *
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# CRG ----------------------------------------------------------------------------------------------
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class _CRG(Module):
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def __init__(self, platform, sys_clk_freq, x5_clk_freq):
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self.clock_domains.cd_sys = ClockDomain()
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# # #
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# clk / rst
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clk = clk12 = platform.request("clk12")
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rst_n = platform.request("rst_n")
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platform.add_period_constraint(clk12, 1e9/12e6)
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if x5_clk_freq is not None:
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clk = clk50 = platform.request("ext_clk50")
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self.comb += platform.request("ext_clk50_en").eq(1)
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platform.add_period_constraint(clk50, 1e9/x5_clk_freq)
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# pll
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self.submodules.pll = pll = ECP5PLL()
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self.comb += pll.reset.eq(~rst_n)
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pll.register_clkin(clk, x5_clk_freq or 12e6)
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pll.create_clkout(self.cd_sys, sys_clk_freq)
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self.specials += AsyncResetSynchronizer(self.cd_sys, ~rst_n)
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# BaseSoC ------------------------------------------------------------------------------------------
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class BaseSoC(SoCCore):
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def __init__(self, sys_clk_freq=int(50e6), x5_clk_freq=None, toolchain="diamond", **kwargs):
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platform = ecp5_evn.Platform(toolchain=toolchain)
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# SoCCore ----------------------------------------------------------------------------------
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SoCCore.__init__(self, platform, clk_freq=sys_clk_freq, **kwargs)
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# CRG --------------------------------------------------------------------------------------
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crg = _CRG(platform, sys_clk_freq, x5_clk_freq)
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self.submodules.crg = crg
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# Build --------------------------------------------------------------------------------------------
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def main():
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parser = argparse.ArgumentParser(description="LiteX SoC on ECP5 Evaluation Board")
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parser.add_argument("--gateware-toolchain", dest="toolchain", default="diamond",
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help='gateware toolchain to use, diamond (default) or trellis')
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builder_args(parser)
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soc_core_args(parser)
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parser.add_argument("--sys-clk-freq", default=60e6,
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help="system clock frequency (default=60MHz)")
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parser.add_argument("--x5-clk-freq", type=int,
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help="use X5 oscillator as system clock at the specified frequency")
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args = parser.parse_args()
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cls = BaseSoC
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soc = cls(toolchain=args.toolchain,
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sys_clk_freq = int(float(args.sys_clk_freq)),
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x5_clk_freq = args.x5_clk_freq,
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**soc_core_argdict(args))
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builder = Builder(soc, **builder_argdict(args))
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builder.build()
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if __name__ == "__main__":
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main()
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