| .. |
|
__init__.py
|
Avoid Official/Partner/Community differentiation: use same directory for all platforms/targets.
|
2020-02-03 09:36:30 +01:00 |
|
ac701.py
|
targets: avoid direct use of mem_decoder.
|
2020-02-11 21:59:42 +01:00 |
|
aller.py
|
Avoid Official/Partner/Community differentiation: use same directory for all platforms/targets.
|
2020-02-03 09:36:30 +01:00 |
|
arty.py
|
platforms/targets: keep in sync with LiteX
|
2020-02-27 11:06:53 +01:00 |
|
c10lprefkit.py
|
targets: avoid direct use of mem_decoder.
|
2020-02-11 21:59:42 +01:00 |
|
camlink_4k.py
|
Avoid Official/Partner/Community differentiation: use same directory for all platforms/targets.
|
2020-02-03 09:36:30 +01:00 |
|
colorlight_5a_75b.py
|
targets/colorlight_5a_75b: add instruction to build/load and use bitstream with wishbone-tool
|
2020-02-25 12:47:08 +01:00 |
|
de0nano.py
|
Avoid Official/Partner/Community differentiation: use same directory for all platforms/targets.
|
2020-02-03 09:36:30 +01:00 |
|
de1soc.py
|
Avoid Official/Partner/Community differentiation: use same directory for all platforms/targets.
|
2020-02-03 09:36:30 +01:00 |
|
de2_115.py
|
Avoid Official/Partner/Community differentiation: use same directory for all platforms/targets.
|
2020-02-03 09:36:30 +01:00 |
|
de10lite.py
|
targets: avoid direct use of mem_decoder.
|
2020-02-11 21:59:42 +01:00 |
|
de10nano.py
|
Avoid Official/Partner/Community differentiation: use same directory for all platforms/targets.
|
2020-02-03 09:36:30 +01:00 |
|
ecp5_evn.py
|
Avoid Official/Partner/Community differentiation: use same directory for all platforms/targets.
|
2020-02-03 09:36:30 +01:00 |
|
fomu.py
|
Changed wrong imports for fomu board.
|
2020-02-12 12:40:07 +01:00 |
|
genesys2.py
|
Avoid Official/Partner/Community differentiation: use same directory for all platforms/targets.
|
2020-02-03 09:36:30 +01:00 |
|
hadbadge.py
|
Avoid Official/Partner/Community differentiation: use same directory for all platforms/targets.
|
2020-02-03 09:36:30 +01:00 |
|
kc705.py
|
targets/kc705: use DDRPHY_CMD_DELAY to center write leveling.
|
2020-02-27 12:58:52 +01:00 |
|
kcu105.py
|
targets/EthernetSoC: be sure memory region is added before adding Wishbone Slave (required by new SoC)
|
2020-02-11 17:45:35 +01:00 |
|
kx2.py
|
Avoid Official/Partner/Community differentiation: use same directory for all platforms/targets.
|
2020-02-03 09:36:30 +01:00 |
|
linsn_rv901t.py
|
targets/EthernetSoC: be sure memory region is added before adding Wishbone Slave (required by new SoC)
|
2020-02-11 17:45:35 +01:00 |
|
mimas_a7.py
|
targets/EthernetSoC: be sure memory region is added before adding Wishbone Slave (required by new SoC)
|
2020-02-11 17:45:35 +01:00 |
|
minispartan6.py
|
Avoid Official/Partner/Community differentiation: use same directory for all platforms/targets.
|
2020-02-03 09:36:30 +01:00 |
|
nereid.py
|
Avoid Official/Partner/Community differentiation: use same directory for all platforms/targets.
|
2020-02-03 09:36:30 +01:00 |
|
netv2.py
|
targets/EthernetSoC: be sure memory region is added before adding Wishbone Slave (required by new SoC)
|
2020-02-11 17:45:35 +01:00 |
|
nexys4ddr.py
|
targets/EthernetSoC: be sure memory region is added before adding Wishbone Slave (required by new SoC)
|
2020-02-11 17:45:35 +01:00 |
|
nexys_video.py
|
Avoid Official/Partner/Community differentiation: use same directory for all platforms/targets.
|
2020-02-03 09:36:30 +01:00 |
|
orangecrab.py
|
Avoid Official/Partner/Community differentiation: use same directory for all platforms/targets.
|
2020-02-03 09:36:30 +01:00 |
|
pipistrello.py
|
Avoid Official/Partner/Community differentiation: use same directory for all platforms/targets.
|
2020-02-03 09:36:30 +01:00 |
|
simple.py
|
targets/EthernetSoC: be sure memory region is added before adding Wishbone Slave (required by new SoC)
|
2020-02-11 17:45:35 +01:00 |
|
tagus.py
|
Avoid Official/Partner/Community differentiation: use same directory for all platforms/targets.
|
2020-02-03 09:36:30 +01:00 |
|
trellisboard.py
|
targets/EthernetSoC: be sure memory region is added before adding Wishbone Slave (required by new SoC)
|
2020-02-11 17:45:35 +01:00 |
|
ulx3s.py
|
Avoid Official/Partner/Community differentiation: use same directory for all platforms/targets.
|
2020-02-03 09:36:30 +01:00 |
|
vc707.py
|
vc707: fix copyrights (Michael Betz is the initial author)
|
2020-02-28 08:39:52 +01:00 |
|
vcu118.py
|
vc707: cleanup platform/targets, remove Ethernet support (no Ethernet pads defined)
|
2020-02-25 10:35:18 +01:00 |
|
versa_ecp5.py
|
targets/EthernetSoC: be sure memory region is added before adding Wishbone Slave (required by new SoC)
|
2020-02-11 17:45:35 +01:00 |
|
zcu104.py
|
zcu104: add separate ddram_32/64 definitions and use ddram_32 for now.
|
2020-02-27 10:05:17 +01:00 |
b44885d222