Florent Kermarrec b6c5a85b98 Add initial Efinix Trion T20 MIPI Dev Kit support: CPU, ROM, RAM, UART and SPI Flash. ... Tested with: ./efinix_trion_t20_mipi_dev_kit.py --with-spi-flash --build --load __ _ __ _ __ / / (_) /____ | |/_/ / /__/ / __/ -_)> < /____/_/\__/\__/_/|_| Build your hardware, easily! (c) Copyright 2012-2021 Enjoy-Digital (c) Copyright 2007-2015 M-Labs BIOS built on Nov 12 2021 08:37:48 BIOS CRC passed (2bec12a3) Migen git sha1: 7507a2b LiteX git sha1: f679992f --=============== SoC ==================-- CPU: VexRiscv @ 100MHz BUS: WISHBONE 32-bit @ 4GiB CSR: 32-bit data ROM: 128KiB SRAM: 8KiB FLASH: 4096KiB --========== Initialization ============-- Initializing W25Q32JV SPI Flash @0x00400000... Enabling Quad mode... First SPI Flash block erased, unable to perform freq test. Memspeed at 0x400000 (Sequential, 4.0KiB)... Read speed: 2.6MiB/s Memspeed at 0x400000 (Random, 4.0KiB)... Read speed: 1.5MiB/s --============== Boot ==================-- Booting from serial... Press Q or ESC to abort boot completely. sL5DdSMmkekro Timeout No boot medium found --============= Console ================-- litex>		2021-11-12 08:42:10 +01:00
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platforms	Add initial Efinix Trion T20 MIPI Dev Kit support: CPU, ROM, RAM, UART and SPI Flash.	2021-11-12 08:42:10 +01:00
prog	prog/openocd_butterstick: Set _CHIPNAME to ecp5 (for jtag_uart/jtag_bone).	2021-10-27 17:27:07 +02:00
targets	Add initial Efinix Trion T20 MIPI Dev Kit support: CPU, ROM, RAM, UART and SPI Flash.	2021-11-12 08:42:10 +01:00
tools
__init__.py	Add initial Fairwaves XTRX support (SoC with JTAG-UART and PCIe Gen2 X1).	2021-11-05 14:52:45 +01:00