Florent Kermarrec b9ac72cf78 targets: simplify clocking on iCE40/ECP5 targets (AsyncResetSynchronizer now integrated in PLL).		2020-09-01 13:38:32 +02:00
..
platforms	orangecrab: reduce DDR3 power consumption/heat and get back USB PLL to CRGSDRAM.	2020-08-28 20:01:54 +02:00
prog	platforms/genesys2: add openocd specific configuration (channel 1 used for JTAG).	2020-06-23 11:55:50 +02:00
targets	targets: simplify clocking on iCE40/ECP5 targets (AsyncResetSynchronizer now integrated in PLL).	2020-09-01 13:38:32 +02:00
tools	general: add SPDX License identifier to header and specify files are part of LiteX-Boards.	2020-08-23 15:00:17 +02:00
__init__.py