litex-boards/litex_boards
2021-12-22 03:28:13 +01:00
..
platforms zedboard: compress bitstream, derive default clk f 2021-12-22 03:13:30 +01:00
prog prog/openocd_butterstick: Set _CHIPNAME to ecp5 (for jtag_uart/jtag_bone). 2021-10-27 17:27:07 +02:00
targets zedboard: disable soc uart for all variants (zynq does not need it, for soft cpus there are no pins) 2021-12-22 03:28:13 +01:00
tools
__init__.py efinix_trion_t120_bga576_dev_kit: Remove debug, integrate LPDDR3 as done on other targets. 2021-11-12 18:04:30 +01:00