156 lines
5.4 KiB
Python
Executable File
156 lines
5.4 KiB
Python
Executable File
#!/usr/bin/env python3
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# This file is Copyright (c) 2019 Antti Lukats <antti.lukats@gmail.com>
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# This file is Copyright (c) 2019 msloniewski <marcin.sloniewski@gmail.com>
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# This file is Copyright (c) 2019 Florent Kermarrec <florent@enjoy-digital.fr>
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# License: BSD
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import argparse
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from migen import *
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from litex_boards.platforms import c10lprefkit
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from litex.soc.integration.soc_core import *
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from litex.soc.integration.soc_sdram import *
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from litex.soc.integration.builder import *
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from litedram.modules import MT48LC16M16
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from litedram.phy import GENSDRPHY
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from liteeth.phy.mii import LiteEthPHYMII
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from liteeth.mac import LiteEthMAC
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from litex.soc.cores.hyperbus import HyperRAM
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# CRG ----------------------------------------------------------------------------------------------
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class _CRG(Module):
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def __init__(self, platform):
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self.clock_domains.cd_sys = ClockDomain()
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self.clock_domains.cd_sys_ps = ClockDomain()
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self.clock_domains.cd_por = ClockDomain(reset_less=True)
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# # #
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self.cd_sys.clk.attr.add("keep")
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self.cd_sys_ps.clk.attr.add("keep")
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self.cd_por.clk.attr.add("keep")
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clk12 = platform.request("clk12")
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# power on rst
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rst_n = Signal()
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self.sync.por += rst_n.eq(platform.request("cpu_reset"))
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self.comb += [
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self.cd_por.clk.eq(clk12),
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self.cd_sys.rst.eq(~rst_n),
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self.cd_sys_ps.rst.eq(~rst_n)
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]
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# sys clk / sdram clk
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clk_outs = Signal(5)
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self.specials += \
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Instance("ALTPLL",
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p_BANDWIDTH_TYPE="AUTO",
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p_CLK0_DIVIDE_BY=6,
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p_CLK0_DUTY_CYCLE=50,
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p_CLK0_MULTIPLY_BY=25,
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p_CLK0_PHASE_SHIFT="0",
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p_CLK1_DIVIDE_BY=6,
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p_CLK1_DUTY_CYCLE=50,
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p_CLK1_MULTIPLY_BY=25,
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p_CLK1_PHASE_SHIFT="-10000",
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p_COMPENSATE_CLOCK="CLK0",
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p_INCLK0_INPUT_FREQUENCY=83000,
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p_INTENDED_DEVICE_FAMILY="MAX 10",
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p_LPM_TYPE="altpll",
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p_OPERATION_MODE="NORMAL",
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i_INCLK=clk12,
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o_CLK=clk_outs,
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i_ARESET=0,
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i_CLKENA=0x3f,
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i_EXTCLKENA=0xf,
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i_FBIN=1,
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i_PFDENA=1,
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i_PLLENA=1,
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)
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self.comb += self.cd_sys.clk.eq(clk_outs[0])
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self.comb += self.cd_sys_ps.clk.eq(clk_outs[1])
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self.comb += platform.request("sdram_clock").eq(self.cd_sys_ps.clk)
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# BaseSoC ------------------------------------------------------------------------------------------
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class BaseSoC(SoCSDRAM):
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mem_map = {
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"hyperram": 0x20000000,
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}
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mem_map.update(SoCCore.mem_map)
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def __init__(self, sys_clk_freq=int(50e6), **kwargs):
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assert sys_clk_freq == int(50e6)
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platform = c10lprefkit.Platform()
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SoCSDRAM.__init__(self, platform, clk_freq=sys_clk_freq,
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integrated_rom_size=0x8000,
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**kwargs)
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self.submodules.crg = _CRG(platform)
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self.submodules.hyperram = HyperRAM(platform.request("hyperram"))
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self.add_wb_slave(mem_decoder(self.mem_map["hyperram"]), self.hyperram.bus)
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self.add_memory_region("hyperram", self.mem_map["hyperram"], 8*1024*1024)
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if not self.integrated_main_ram_size:
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self.submodules.sdrphy = GENSDRPHY(platform.request("sdram"))
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sdram_module = MT48LC16M16(self.clk_freq, "1:1")
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self.register_sdram(self.sdrphy,
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sdram_module.geom_settings,
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sdram_module.timing_settings)
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class EthernetSoC(BaseSoC):
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mem_map = {
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"ethmac": 0x30000000, # (shadow @0xb0000000)
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}
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mem_map.update(BaseSoC.mem_map)
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def __init__(self, eth_port=0, **kwargs):
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BaseSoC.__init__(self, **kwargs)
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self.submodules.ethphy = LiteEthPHYMII(self.platform.request("eth_clocks", eth_port),
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self.platform.request("eth", eth_port))
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self.add_csr("ethphy")
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self.submodules.ethmac = LiteEthMAC(phy=self.ethphy, dw=32,
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interface="wishbone", endianness=self.cpu.endianness)
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self.add_wb_slave(self.mem_map["ethmac"], self.ethmac.bus, 0x2000)
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self.add_memory_region("ethmac", self.mem_map["ethmac"] | self.shadow_base, 0x2000)
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self.add_csr("ethmac")
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self.add_interrupt("ethmac")
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self.platform.add_period_constraint(self.platform.lookup_request("eth_clocks").tx, 1e9/12.5e6)
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self.platform.add_period_constraint(self.platform.lookup_request("eth_clocks").rx, 1e9/12.5e6)
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self.platform.add_false_path_constraints(
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self.platform.lookup_request("clk12"),
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self.platform.lookup_request("eth_clocks").tx,
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self.platform.lookup_request("eth_clocks").rx
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)
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# Build --------------------------------------------------------------------------------------------
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def main():
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parser = argparse.ArgumentParser(description="LiteX SoC on C10 LP RefKit")
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builder_args(parser)
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soc_sdram_args(parser)
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parser.add_argument("--with-ethernet", action="store_true",
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help="enable Ethernet support")
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args = parser.parse_args()
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cls = EthernetSoC if args.with_ethernet else BaseSoC
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soc = cls(**soc_sdram_argdict(args))
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builder = Builder(soc, **builder_argdict(args))
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builder.build()
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if __name__ == "__main__":
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main()
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